ADV3203 AD [Analog Devices], ADV3203 Datasheet
ADV3203
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ADV3203 Summary of contents
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... SWITCHES Figure 1. an output bus if building a larger array. The ADV3202 has a gain of +1 while the ADV3203 has a gain of +2 for ease of use in back-terminated load applications. A single +5 V supply, dual ±2.5 V supplies, or dual ±3.3 V supplies (G = +2) can be used while consuming only 195 mA of idle current with all outputs enabled ...
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... ADV3202/ADV3203 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 OSD Disabled ................................................................................ 3 OSD Enabled ................................................................................. 4 Timing Characteristics (Serial Mode) ....................................... 5 Absolute Maximum Ratings ............................................................ 6 Thermal Resistance ...................................................................... 6 REVISION HISTORY 10/08—Revision 0: Initial Version Power Dissipation..........................................................................6 ESD Caution...................................................................................6 Pin Configuration and Function Descriptions ..............................7 ...
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... V Sync-tip clamp enabled, V Sync-tip clamp disabled SWITCHING CHARACTERISTICS Enable On Time 50% update to 1% settling Switching Time Step 50% update to 1% settling Switching Transient (Glitch) IN00 to IN31, RTI = 25° (ADV3202 (ADV3203 Min = 150 Ω kΩ 150 Ω kΩ ...
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... NEG outputs disabled POS NEG VCC − V POS NEG , MHz NEG POS = 25° (ADV3202 (ADV3203 Conditions 200 mV p p-p 0.1 dB, 200 mV p-p 0.1 dB p-p 1 step 2 V step, peak NTSC or PAL NTSC or PAL 0.5 MHz to 50 MHz No load Sync-tip clamp disabled 50% OSD switch to 1% settling Rev ...
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... TRANSFER DATA FROM SERIAL LATCHES DURING LOW LEVEL t 7 Figure 2. Timing Diagram, Serial Mode DATA OUT RESET, CS, CLK, DATA IN, UPDATE, OSDS 0.5 V max 0.5 μA typ Rev Page ADV3202/ADV3203 Limit Typ Max 50 160 130 50 38.6 160 OUT00 (D0 REGISTER TO PARALLEL ...
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... Package Type 176-Lead LQFP_EP POWER DISSIPATION The ADV3202/ADV3203 are operated with ±2 ±3.3 V supplies and can drive loads down to 150 Ω, resulting in a large range of possible power dissipations. For this reason, extra care must be taken while derating the operating conditions based on ambient temperature ...
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... OSD15 44 NOTES CONNECT 2. OSDS#: OSD SELECT FOR OUTPUT # OSD#: OSD VIDEO INPUT FOR OUTPUT # 3. THE EXPOSED PAD SHOULD BE CONNECTED TO ANALOG GROUND. ADV3202/ADV3203 TOP VIEW (Not to Scale) Figure 4. Pin Configuration Rev Page ADV3202/ADV3203 VNEG 132 NC 131 NC 130 NC 129 NC 128 NC 127 ...
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... ADV3202/ADV3203 Table 7. Pin Function Descriptions Pin Mnemonic Description 1 DVCC Digital Positive Power Supply Connect RESET Control Pin CLK Control Pin: Serial Data Clock. 5 DATA IN Control Pin: Serial Data In. 6 DATA OUT Control Pin: Serial Data Out. 7 UPDATE Control Pin: Second Rank Write Strobe. ...
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... Analog Positive Power Supply. 169 NC No Connect. 170 NC No Connect. 171 NC No Connect. 172 NC No Connect. 173 NC No Connect. 174 NC No Connect. 175 NC No Connect. 176 DGND Digital Negative Power Supply. EPAD Connect to analog ground. (exposed pad) Rev Page ADV3202/ADV3203 ...
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... ADV3202/ADV3203 TRUTH TABLE AND LOGIC DIAGRAM Table 8. Operation Truth Table CS UPDATE CLK DATA INPUT Data Data : serial data. i RESET DATA OUTPUT Operation/Comment X 0 Asynchronous reset. All outputs are disabled; the 193-bit shift register is reset to all 0s. ...
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... TYPICAL PERFORMANCE CHARACTERISTICS V = ±2.5 V (ADV3202 ±3.3 V (ADV3203 –2 OSDxx –4 –6 –8 –10 – FREQUENCY (MHz) Figure 5. ADV3202 Small Signal Frequency Response, 200 mV p –2 –4 –6 –8 –10 – FREQUENCY (MHz) Figure 6. ADV3202 Large Signal Frequency Response p-p ...
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... TIME (ns) Figure 14. ADV3203 Small Signal Pulse Response, 200 mV p-p 1.2 0.8 0.4 0 –0.4 –0.8 INxx –1 TIME (ns) Figure 15. ADV3203 Large Signal Pulse Response p-p 600 400 RISING EDGE 200 0 –200 FALLING EDGE –400 –600 TIME (ns) Figure 16 ...
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... INPUT DC OFFSET (V) Figure 17. ADV3203 Differential Gain, Carrier Frequency = 3.58 MHz, Subcarrier Amplitude = 300 mV p-p 0.05 0.04 0.03 0.02 0.01 0 –0.01 –0.02 –0.03 –0.04 –0.05 –0.7 –0.5 –0.3 –0.1 0.1 INPUT DC OFFSET (V) Figure 18. ADV3203 Differential Phase, Carrier Frequency = 3.58 MHz, Subcarrier Amplitude = 300 mV p-p ...
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... VNEG VPOS VREF VNEG Figure 20. Conceptual Diagram of Single Output Channel (ADV3203) Each input to the ADV3202/ADV3203 is buffered by a receiver. The purpose of this receiver is to provide overvoltage protection for the input stages by limiting signal swing. In the ADV3202, the output of the receiver is limited to ±1.2 V about VREF, while in the ADV3203, the signal swing is limited to ± ...
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... VPOS/VNEG supply pins) and the control logic interface (with the VDD/DGND supply pins). However, to easily interface to ground referenced video signals, split supply operation is possible with ±2.5 V. (The ADV3203 is intended to operate on ±3.3 V.) In the case of split supplies, a flexible logic interface allows the control logic supplies (VDD/DGND run off +3 ...
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... The UPDATE latches are asynchronous and when UPDATE is low, they are transparent. If more than one ADV3202/ADV3203 device serially programmed in a system, the DATA OUT signal from one device can be connected to the DATA IN of the next device to form a serial chain ...
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... COMPLIANT TO JEDEC STANDARDS MS-026-BGA-HD (SW-176-1) Dimensions shown in millimeters Package Description 176-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP] 176-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP] Rev Page ADV3202/ADV3203 21.50 REF 133 176 132 1 EXPOSED PAD BOTTOM VIEW ...
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... ADV3202/ADV3203 NOTES Rev Page ...
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... NOTES Rev Page ADV3202/ADV3203 ...
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... ADV3202/ADV3203 NOTES ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07526-0-10/08(0) Rev Page ...