PGA203AG BURR-BROWN [Burr-Brown Corporation], PGA203AG Datasheet - Page 7

• Manufacturer Part Number: PGA203AG
• Description: Digitally Controlled Programmable-Gain INSTRUMENTATION AMPLIFIER
• Manufacturer: BURR-BROWN [Burr-Brown Corporation]

TYPICAL PERFORMANCE
CURVES
T
DISCUSSION OF
PERFORMANCE
A simplified diagram of the PGA202/203 is shown on the
first page. The design consists of a digitally controlled,
differential transconductance front end stage using precision
FET buffers and the classical transimpedance output stage.
Gain switching is accomplished with a novel current steer-
ing technique that allows for fast settling when changing
gains. The result is a high performance, programmable
instrumentation amplifier with excellent speed and gain
accuracy.
The input stage uses a new circuit topology that includes
FET buffers to give extremely low input bias currents. The
differential input voltage is converted into a differential
output current with the transconductance gain selected by
steering the input stage bias current between four identical
input stages differing only in the value of the gain setting
resistor. Each input stage is individually laser-trimmed for
input offset, offset drift, and gain.
The output stage is a differential transimpedance amplifier.
Unlike the classical difference amplifier output stage, the
common-mode rejection is not limited by the resistor match-
ing. However, the output resistors are laser-trimmed to help
minimize the output offset and drift.
BASIC CONNECTIONS
Figure 1 shows the proper connections for power supply and
signal. The power supplies should be decoupled with 1 F
tantalum capacitors placed as close to the amplifier as
possible for maximum performance. To avoid gain and
CMR errors introduced by the external components, you
should connect the grounds as indicated. Any resistance in
the sense line (pin 11) or the V
a gain error, so these lines should be kept as short as
possible. To also maintain stability, avoid capacitance from
the output to the input or the offset adjust pins.
A
= +25 C, V
CC
= 15V unless otherwise noted.
(CONT)
SMALL SIGNAL RESPONSE
1µs/Div
G = 10
REF
line (pin 4) will lead to
7
FIGURE 1. Basic Circuit Connections.
OFFSET ADJUSTMENT
Figure 2 shows the offset adjustment circuits for the PGA202/
203. The input offset and the output offset are both sepa-
rately adjustable. Notice that because the PGA202/203 change
between four different input stages to change gain, the input
offset voltage will change slightly with gain. For systems
using computer autozeroing techniques, neither offset nor
drift is a major concern, but it should be noted that since the
input offset does change with gain, these systems should
perform an autozero cycle after each gain change for opti-
mum performance.
In the output offset adjustment circuit, the choice of the
buffering op amp is very important. The op amp needs to
have low output impedance and a wide bandwidth to main-
tain full accuracy over the entire frequency range of the
PGA202/203. For these reasons we recommend the OPA602
as an excellent choice for this application.
FIGURE 2. Offset Adjustment Circuits.
V
IN
V
IN
8
7
8
7
+V
+
–
PGA202
6
50k
+
–
+V
CC
D
1
3
PGA202
IN
CC
4
OPA602
9
2
–V
CC
PGA202/203
14
13
11 12
+
–
11
4
12
100k
100
V
OUT
R
+V
–V
L
V
CC
CC
OUT
10k
®