CLC1200IDP8 CADEKA [Cadeka Microcircuits LLC.], CLC1200IDP8 Datasheet - Page 13
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CLC1200IDP8
Manufacturer Part Number
CLC1200IDP8
Description
Instrumentation Amplifier
Manufacturer
CADEKA [Cadeka Microcircuits LLC.]
Datasheet
1.CLC1200IDP8.pdf
(15 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CLC1200IDP8
Manufacturer:
CADEKA
Quantity:
20 000
Data Sheet
Grounding
The output voltage of the CLC1200 is developed with
respect to the potential on the reference terminal (pin 8).
Simply tie the REF pin to the appropriate “local ground” to
resolve many grounding problems.
To isolate low level analog signals from a noisy digital
environment, many data-aquisistion components have
separate analog and digital ground pins. Use separate
ground lines (analog and digital) to minimize current flow
from sensitive areas to system ground. These ground
returns must be tied together at some point, usually best
at the ADC.
Layout Considerations
General layout and supply bypassing play major roles in
high frequency performance. CADEKA has evaluation
boards to use as a guide for high frequency layout and as
an aid in device testing and characterization. Follow the
steps below as a basis for high frequency layout:
▪
▪
▪
▪
▪
Refer to the evaluation board layouts below for more
information.
Evaluation Board Information
The following evaluation boards are available to aid in the
testing and layout of these devices:
Evaluation Board Schematics
Evaluation board schematics and layouts are shown in
Figures 5-7. These evaluation boards are built for dual-
supply operation. Follow these steps to use the board in a
single-supply application:
1. Short -Vs to ground.
2. Use C3 and C4, if the -V
©2008, 2010-2011 CADEKA Microcircuits LLC
CEB024
Evaluation Board
Include 6.8µF and 0.1µF ceramic capacitors for power
supply decoupling
Place the 6.8µF capacitor within 0.75 inches of the power pin
Place the 0.1µF capacitor within 0.1 inches of the power pin
Remove the ground plane under and around the part,
especially near the input and output pins to reduce
parasitic capacitance
Minimize all trace lengths to reduce series inductances
directly connected to the ground plane.
#
CLC1200 in SOIC-8
S
pin of the amplifier is not
Products
Figure 7. CEB024 Bottom View
Figure 5. CEB00x Schematic
Figure 6. CEB024 Top View
www.cadeka.com
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