LMV712MMX NSC [National Semiconductor], LMV712MMX Datasheet - Page 10

• Manufacturer Part Number: LMV712MMX
• Description: Low Power, Low Noise, High Output, RRIO Dual Operational Amplifier with Independent Shutdown
• Manufacturer: NSC [National Semiconductor]

www.national.com
Application Information
Theory of Operation
The LMV712 dual op amp is derived from the LMV711 single
op amp. Figure 1 contains a simplified schematic of one
channel of the LMV712.
Rail-to-Rail input is achieved by using in parallel, one NMOS
differential pair (MN1 and MN2) and one PMOS differential
pair (MP1 and MP2). When the common mode input voltage
(V
off. When V
PMOS pair is on. When V
logic decides how much current each differential pair will get.
This special logic ensures stable and low distortion amplifier
operation within the entire common mode voltage range.
Because both input stages have their own offset voltage
(V
comes a function of V
above V
Performance Characteristics section. Caution should be
taken in situations where input signal amplitude is compa-
rable to V
In these situations, it is necessary for the input signal to
avoid the crossover point.
The current coming out of the input differential pairs gets
mirrored through two folded cascode stages (Q1, Q2, Q3,
Q4) into the ’class AB control’ block. This circuitry generates
voltage gain, defines the op amp’s dominant pole and limits
the maximum current flowing at the output stage. MN3 intro-
duces a voltage level shift and acts as a high impedance to
low impedance buffer.
The output stage is composed of a PMOS and a NPN
transistor in a common source/emitter configuration, deliver-
ing a rail-to-rail output excursion.
The MN4 transistor ensures that the LMV712 output remains
near V
Shutdown Pin
The LMV712 offers independent shutdown pins for the dual
amplifiers. When the shutdown pin is tied low, the respective
amplifier shuts down and the supply current is reduced to
less than 1µA. In shutdown mode, the amplifier’s output level
stays at V
1.5V to 2.7V is applied to the shutdown pin, the amplifier is
enabled. As the amplifier is coming out of the shutdown
mode, the output waveform ramps up without any glitch. This
is demonstrated in Figure 2 .
CM
OS
) characteristic, the offset voltage of the LMV712 be-
) is near V
−
−
when the amplifier is in shutdown mode.
. Refer to the ’V
OS
−
. In a 2.7V operation, when a voltage between
CM
value and/or the design requires high accuracy.
+
, the NMOS pair is on and the PMOS pair is
is near V
CM
FIGURE 1.
. V
CM
−
OS
, the NMOS pair is off and the
OS
is between V
vs. V
has a crossover point at 1.4V
CM
’ curve in the Typical
+
and V
−
, internal
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A glitch-free output waveform is highly desirable in many
applications, one of which is power amplifier control loops. In
this application, the LMV712 is used to drive the power
amplifier’s power control. If the LMV712 did not have a
smooth output ramp during turn on, it would directly cause
the power amplifier to produce a glitch at its output. This
adversely affects the performance of the system.
To enable the amplifier, the shutdown pin must be pulled
high. It should not be left floating in the event that any
leakage current may inadvertently turn off the amplifier.
Printed Circuit Board Consideration
To properly bypass the power supply, several locations on a
printed circuit board need to be considered. A 6.8µF or
greater tantalum capacitor should be placed at the point
where the power supply for the amplifier is introduced onto
the board. Another 0.1µF ceramic capacitor should be
placed as close as possible to the power supply pin of the
amplifier. If the amplifier is operated in a single power supply,
only the V
If the amplifier is operated in a dual power supply, both V
and V
It is good practice to use a ground plane on a printed circuit
board to provide all components with a low inductive ground
connection.
Surface mount components in 0805 size or smaller are
recommended in the LMV712 application circuits. Designers
can take advantage of the micro SMD, MSOP and LLP
miniature sizes to condense board layout in order to save
space and reduce stray capacitance.
Capacitive Load Tolerance
The LMV712 can directly drive 200pF in unity-gain without
oscillation. The unity-gain follower is the most sensitive con-
figuration to capacitive loading. Direct capacitive loading
reduces the phase margin of amplifiers. The combination of
the amplifier’s output impedance and the capacitive load
induces phase lag. This results in either an under-damped
pulse response or oscillation. To drive a heavier capacitive
load, Figure 3 can be used.
−
pins need to be bypassed.
+
pin needs to be bypassed with a 0.1µF capacitor.
FIGURE 2.
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+