74ACT573M STMICROELECTRONICS [STMicroelectronics], 74ACT573M Datasheet

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74ACT573M

Manufacturer Part Number
74ACT573M
Description
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS (NON INVERTED)
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet

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DESCRIPTION
The 74ACT573 is an advanced high-speed CMOS
OCTAL D-TYPE LATCH with 3 STATE OUTPUT
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C
technology.
These 8 bit D-Type latch are controlled by a latch
enable input (LE) and an output enable input (OE).
While the LE inputs is held at a high level, the Q
outputs will follow the data input .
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 2001
HIGH SPEED: t
LOW POWER DISSIPATION:
I
COMPATIBLE WITH TTL OUTPUTS
V
50 TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
BALANCED PROPAGATION DELAYS:
t
OPERATING VOLTAGE RANGE:
V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 573
IMPROVED LATCH-UP IMMUNITY
CC
PLH
OH
IH
CC
= 4 A(MAX.) at T
= 2V (MIN.), V
| = I
(OPR) = 4.5V to 5.5V
t
PHL
OL
= 24mA (MIN)
PD
IL
= 5ns (TYP.) at V
= 0.8V (MAX.)
A
=25°C
WITH 3 STATE OUTPUTS (NON INVERTED)
CC
= 5V
2
MOS
ORDER CODES
When the LE is taken low, the Q outputs will be
latched precisely or inversely at the logic level of D
input data. While the (OE) input is low, the 8
outputs will be in a normal logic state (high or low
logic level) and while high level the outputs will be
in a high impedance state.
This device is designed to interface directly High
Speed CMOS systems with TTL and NMOS
components.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PACKAGE
TSSOP
SOP
DIP
DIP
OCTAL D-TYPE LATCH
74ACT573M
74ACT573B
TUBE
SOP
74ACT573
74ACT573MTR
74ACT573TTR
TSSOP
T & R
1/11

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74ACT573M Summary of contents

Page 1

... This device is designed to interface directly High 2 MOS Speed CMOS systems with TTL and NMOS components. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. 74ACT573 SOP TSSOP TUBE T & R 74ACT573B 74ACT573M 74ACT573MTR 74ACT573TTR 1/11 ...

Page 2

INPUT AND OUTPUT EQUIVALENT CIRCUIT TRUTH TABLE Don’t care Z : High Impedance NOTE: Outputs are latched at the time when the input is taken LOW logic level LOGIC DIAGRAM This logic ...

Page 3

ABSOLUTE MAXIMUM RATINGS Symbol V Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Current ...

Page 4

DC SPECIFICATIONS Symbol Parameter V V High Level Input IH Voltage V Low Level Input IL Voltage V High Level Output OH Voltage V Low Level Output OL Voltage I Input Leakage Cur- I rent I High Impedance OZ ...

Page 5

CAPACITIVE CHARACTERISTICS Symbol Parameter V C Input Capacitance IN Output C OUT Capacitance C Power Dissipation PD Capacitance (note defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current ...

Page 6

WAVEFORM PROPAGATION DELAYS, LE MINIMUN PULSE WIDTH SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle) 6/11 ...

Page 7

WAVEFORM 3: PROPAGATION DELAYS TIME (f=1MHz; 50% duty cycle) 74ACT573 7/11 ...

Page 8

Plastic DIP-20 (0.25) MECHANICAL DATA DIM. MIN. a1 0.254 B 1. 8/11 mm TYP. MAX. MIN. 0.010 1.65 0.055 0.45 0.25 25.4 8.5 2.54 22.86 7.1 3.93 3.3 1.34 ...

Page 9

SO-20 MECHANICAL DATA mm DIM. MIN. TYP 0. 0.35 b1 0. 12.60 E 10.00 e 1.27 e3 11.43 F 7. inch MAX. MIN. TYP. 2.65 0.20 0.004 2.45 ...

Page 10

DIM. MIN 0.05 A2 0.85 b 0.19 c 0.09 D 6.4 E 6. PIN 1 IDENTIFICATION 1 10/11 TSSOP20 MECHANICAL DATA mm TYP. MAX. 1.1 ...

Page 11

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. ...

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