MAX8831 MAXIM [Maxim Integrated Products], MAX8831 Datasheet - Page 15

• Manufacturer Part Number: MAX8831
• Description: High-Efficiency, White LED Step-Up Converter with I2C Interface in 2mm x 2mm WLP
• Manufacturer: MAXIM [Maxim Integrated Products]

Figure 5. I
Figure 6. I
The MAX8831 operates as an I
and sends data through an I
interface. The LED1–LED5 current settings, ramp and
blink-rate timers, and other configuration parameters
are set using the I
definitions for more details.
The interface uses a serial-data line (SDA) and a serial-
clock line (SCL) to achieve bidirectional communication
between master(s) and slave(s). A master (typically a
microcontroller) initiates all data transfers to and from
the MAX8831, and generates the SCL clock that syn-
chronizes the data transfer (Figure 5). The MAX8831
SDA line operates as both an input and an open-drain
output. A pullup resistor, typically 4.7kΩ, is required on
SDA. The MAX8831 SCL line operates only as an input.
A pullup resistor, typically 4.7kΩ, is required on SCL if
there are multiple masters on the 2-wire interface, or if
the master in a single-master system has an open-drain
SDA
SCL
t
START CONDITION
HD,STA
SDA
SCL
High-Efficiency, White LED Step-Up Converter
CONDITION
S
2
2
START
C Interface Timing Diagram
C START and STOP Conditions
t
LOW
______________________________________________________________________________________
2
C serial interface. See the register
with I
t
t
SU,DAT
HIGH
2
2
C-compatible, 2-wire
C slave that receives
I
2
2
t
C Interface
HD,DAT
C Interface in 2mm x 2mm WLP
STOP CONDITION
P
t
SU,STA
CONDITION
REPEATED
START
SCL output. Each transmission consists of a START
condition (Figure 6) sent by a master, followed by the
MAX8831 7-bit slave address plus a R/W bit, a register
address byte, 1 or more data bytes, and finally a STOP
condition (Figures 5 and 6).
Both SCL and SDA remain high when the interface is
not busy. The master signals the beginning of a trans-
mission with a START (S) condition by transitioning
SDA from high to low while SCL is high. When the mas-
ter has finished communicating with the slave, it issues
a STOP (P) condition by transitioning the SDA from low
to high while SCL is high. The bus is then free for
another transmission (Figure 6).
One data bit is clocked onto SDA on the falling edge of
SCL and is read on the rising edge of SCL. The data on
the SDA line must remain stable while SCL transitions
(Figure 7).
The acknowledge bit is a clocked 9th bit that the recipi-
ent uses to handshake receipt of each byte of data
(Figure 8). Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse, such that the SDA line is sta-
ble low during the high period of the clock pulse. When
the master is transmitting to the MAX8831, the
MAX8831 generates the acknowledge bit because it is
the recipient. When the MAX8831 is transmitting to the
master, the master generates the acknowledge bit
because it is the recipient.
t
HD,STA
START and STOP Conditions
t
SU,STO
CONDITION
STOP
Acknowledge
Bit Transfer
t
BUF
CONDITION
STOP
15