HD151011FPEL RENESAS [Renesas Technology Corp], HD151011FPEL Datasheet - Page 2

• Manufacturer Part Number: HD151011FPEL
• Description: Dual BCD Programmable Counter with Synchronous Preset Enable
• Manufacturer: RENESAS [Renesas Technology Corp]

HD151011
Function Table
H
X
—
—
L
H
Note:
H :
L :
X :
— :
Pin Arrangement
Rev.2.00, Jul.16.2004, page 2 of 13
CLR
High level
Low level
Immaterial
Irrespective of condition
1. Synchronous preset (SPE) input can set max 99 down counts.
2. When the count value is 0, the next clock pulse presets the data to invert the output.
3. CLR and PR inputs initialize output state.
4. Clock inputs (CLK, CLK) is selectable CMOS level (V
Don't set data exceeding 99 to Jn. (J0 : LSB, J7 : MSB)
H
X
—
—
H
L
Control Inputs
C/T, PR, CLR and SPE inputs are CMOS level)
PR
H
L
—
—
—
—
SPE
SPE
SPE
SPE
X
X
H
L
—
—
C/T T T T
GND
CO
J 0
J 1
J 2
J 3
J 4
J 5
J 6
J 7
Generally count
Synchronous preset
—
—
Initialize of Q output
Initialize of Q output
10
1
4
2
3
5
7
8
9
6
Mode
(Top view)
Down count at the rise edge of clock (CLK)
Down count at the fall edge of clock (CLK)
Jn data is preset at the rise of clock (CLK), the fall of clock
(CLK)
Clock inputs (CLK, CLK) is CMOS level
Clock inputs (CLK, CLK) is TTL level
Initialize of Q = “L”
Initialize of Q = “H”
CC
= 2.0 to 6.0 V) and TTL level (V
16
14
20
19
18
17
15
13
12
11
V
(Test 1)
(Test 2)
C / T
CLK
CLK
Q
PR
SPE
CLR
CC
Operation Description
*
*
CC
= 4.5 to 5.5V) (Jn,