DM9601E ETC1 [List of Unclassifed Manufacturers], DM9601E Datasheet
DM9601E
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DM9601E Summary of contents
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General Description The DM9601 is a fully integrated and cost-effective single chip USB to Fast Ethernet MAC controller with 10/100 PHY designed with the low power and high performance process 3.3V device with 5V ...
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Table of Contents 1. General Description ..............................................1 2. Block Diagram……………………………………… Features ................................................................4 3.1 USB Characteristics............................................4 3.2 Tansceiver ..........................................................4 3.3 Other ...................................................................4 4. Pin Configuration ..................................................5 5. Pin Description......................................................6 5.1 MII Interface ........................................................6 5.2 EEPROM Interface .............................................6 5.3 USB ...
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PHY ID Identifier Register #1 (PHYID1) – 02 .31 11.4 PHY Indentifier Register #2 (PHYID2)-03.......31 11.5 Auto-negotiation Advertisement Register (ANAR)-04 .......................................................32 11.6 Auto-negotiation Link Partner Ability Register (ANLPAR)-05...................................................33 11.7 Auto-negotiation Expansion Register (ANER .....................................................................34 11.8 DAVICOM Specified ...
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Features 3.1 USB Characteristics USB Specification revision 1.1 compliant ■ Supports 12MHz Full-Speed operation ■ Supports suspend mode and remote wake up ■ resume Supports USB standard commands ■ Supports vendor specific commands ■ Supports test-mode for memory test. ...
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Pin Configuration: 100 Pin LQFP & with MII Interface Mode AGND LINK_O 79 WAKEUP 80 PW_RST# 81 DGND 82 GPIO4 GPIO5 83 84 GPIO6 ...
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Pin Description I= Input, O=Output, I/O= Input/Output, O/D= Open Drain, P= Power, LI= reset Latch Input, #= asserted low 5.1 MII Interface Pin No. Pin Name 37 LINK_I 38,39,40, RXD[3: CRS 44 COL 45 RX_DV 46 RX_ER ...
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Clock Interface 21 X2_25M 22 X1_25M 59 CLK20MO 5.5 LED Interface 60 SPEED100# 61 DUP# 62 LINK&ACT# 5.6 10/100 PHY/Fiber AGND 26 BGRES 27 AVDD 28 AVDD 29 RX+ 30 RX- 31 AGND 32 AGND 33 ...
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LINK_O 79 WAKEUP 80 PW_RST# 1,2,3,4,6,7, 8,9,10,11, 12,13,14, 77,85,86, NC 87,88,89, 91,92,93, 94,95,96, 97,98,100 5.8 Power Pins 5,20,36,55, DVDD 72,90, 15,17,18, 19,23,42, DGND 48,58,63, 81,99 73 AVDD 76 AGND 8 USB to Ethernet MAC Controller with Integrated 10/100 PHY ...
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USB Standard Command 6.1 Supported Standard Command BmReqType BRequest 00000000B 00000001B CLEAR_FEATURE 00000010B 10000000B GET_CONFIGURATION 10000000B GET_DESCRIPTOR 10000001B GET_INTERFACE 10000000B 10000001B GET_STATUS 10000010B 00000000B SET_ADDRESS 00000000B SET_CONFIGURATION 00000000B SET_DESCRIPTOR 00000000B 00000001B SET_FEATURE 00000010B 00000001B SET_INTERFACE 10000010B SYNCH_FRAME 6.2 Not ...
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Vendor commands There are two types of vendor’s command. We can access internal register maximum 256 bytes, 7.1 Register Type READ_REGISTER( ) Setup Stage BmReqType bReq Byte 0 Byte 1 Byte 2 C0H 00H WRITE_REGISTER( ) Setup Stage BmReqType ...
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Memory Type These kinds of commands are valid when the bit “MEM_MODE “ is set, otherwise the device will READ_MEMORY( ) Setup Stage BmReqType Breq Byte 0 Byte 1 Byte 2 C0H 02H 00H WRITE_MEMORY( ) Setup Stage BmReqType ...
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Interface 0 Configuration 8.1 Endpoint 1 Type: Bulk In Packet Load: 64-byte When host is accessing EP1. If IN-FIFO is full, device will send 64-byte data. If IN-FIFO isn’t full and Ethernet packet isn’t end, device will send a ...
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Descriptor Values All descriptors are stored in it’s default values. Values which are “?” in the table below are under define. 9.1 Device Descriptor/18-Byte Offset Field Size 0 bLength 1 bDescriptorType 2 bcdUSB 4 bDeviceClass 5 bDeviceSubClass 6 bDeviceProtocol ...
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Configuration0 Descriptor/9-Byte Offset Field Size 0 bLength 1 bDescriptorType 2 wTotalLength 4 bNumInterfaces 5 bConfigurationValue 6 iConfiguration 7 bmAttributes 8 MaxPower 9.3 Interface0 Descriptor/9-Byte Offset Field Size 0 bLength 1 bDescriptorType 2 bInterfaceNumber 3 bAlternateSetting 4 bNumEndpoints 5 bInterfaceClass ...
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Endpoint1 Descriptor/6-Byte Offset Field Size 0 bLength 1 1 bDescriptorType 1 2 bEndpointAddress 1 3 bmAttributes 1 4 wMaxPacketSize 2 6 bInterval 1 Final Version: DM9601-DS-F01 June 22, 2002 USB to Ethernet MAC Controller with Integrated 10/100 PHY Value ...
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Endpoint3 Descriptor/6-Byte Offset Field Size 0 bLength 1 1 bDescriptorType 1 2 bEndpointAddress 1 3 bmAttributes 1 4 wMaxPacketSize 2 6 bInterval 1 9.6 String0 Descriptor/Code array Offset Field Size 0 bLength 1 bDescriptorType 2 wLANGID[1] 16 USB to ...
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String0 Descriptor1/2/3 are loaded from EEPROM String1 Descriptor/UNICODE String Offset Field Size 0 bLength 1 1 bDescriptorType 1 2~ bString n String2 Descriptor/UNICODE String Offset Field Size 0 bLength 1 1 bDescriptorType 1 2~ bString n String3 Descriptor/UNICODE String ...
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Vendor Control and Status Register Set The DM9601 implements several control and status registers, which can be accessed by the USB vendor register type commands. All CRs are set to their default Register NCR Network Control Register NSR Network ...
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Key to Default In the register description that follows, the default column takes the form: <Reset Value>, <Access Type> Where： <Reset Value>: 1 Bit set to logic one 0 Bit set to logic zero X No default value 10.1 Network ...
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TX Control Register (02H) Bit Name Default 7 RESERVED 0,RO 6 TJDIS 0,RW 5 EXCECM 0,RW 4 PAD_DIS2 0,RW 3 CRC_DIS2 0,RW 2 PAD_DIS1 0,RW 1 CRC_DIS1 0,RW 0 RESERVED 0,RO 10.4 TX Status Register I ( 03H ) ...
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TX Status Register II ( 04H ) for packet index I I Bit Name Default 7 TJTO 0,RO 3 COL 0, 0,RO 1:0 RESERVED 0,RO 10.6 RX Control ...
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CE 0,RO 0 FOE 0,RO 10.8 Receive Overflow Counter Register ( 07H ) Bit Name Default 7 RXFU 0,R/C 6:0 ROC 0,R/C 10.9 Back Pressure Threshold Register (08H) Bit Name Default 7:4 BPHW 3h, RW 3:0 JPT 7h, RW ...
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RX/TX Flow Control Register ( 0AH ) Bit Name Default 7 TXP0 0,RW 6 TXPF 0,RW 5 TXPEN 0,RW 4 BKPA 0,RW 3 BKPM 0,RW 2 RXPS 0,R/C 1 RXPCS 0,RO 0 FLCE 0,RW 10.12 EEPROM & PHY Control ...
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Wake Up Control Register ( 0FH ) Bit Name Type 7:6 RESERVED 0,RO 5 LINKEN 0,RW 4 SAMPLEEN 0,RW 3 MAGICEN 0,RW 2 LINKST 0,RO 1 SAMPLEST 0,RO 0 MAGICST 0,RO 10.16 Physical Address Register ( 10H~15H ) Bit ...
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General purpose Register ( 1FH ) Bit Name Default 7 RESERVED 0,RO 6:1 GEPIO6-1 0,RW 0 GEPIO0 1,RW 10.20 TX SRAM Write Pointer Address Register (20H~21H) Bit Name Default 7:0 TWPAH 00H,RO 7:0 TWPAL 00H.RO 10.21 TX SRAM Read ...
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Vendor ID Register (28H~29H) Bit Name Default 7:0 VIDH 0AH,RO 7:0 VIDL 46H.RO 10.25 Product ID Register (2AH~2BH) Bit Name Default 7:0 PIDH 96H,R 7:0 PIDL 01H.R 10.26 Chip Revision Register (2CH) Bit Name Default 7:0 CHIPR 00H,RO 10.27 ...
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USB Control Register (F4H) Bit Name Default 7 Reserved 0,RW 6 Reserved 0,RW 5 EP3ACK 0,RW 4 EP3NAK 0,RW 3 Reserved 0,RW 2 Reserved 0,RW 1 Reserved 0,RW 0 MEMTST 0,RW 10.31 EEPROM Format: name Word MAC address 0 ...
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MII Register Description ADD Name CONTROL Reset Loop Speed back select 01 STATUS T4 TX FDX TX HDX Cap. Cap. Cap. 02 PHYID1 PHYID2 Auto-Neg. Next FLP ...
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Basic Mode Control Register (BMCR Bit Bit Name Default 0.15 Reset 0, RW/SC 0.14 Loopback 0.13 Speed selection Auto- 0.12 negotiation enable 0.11 Power down 0.10 Isolate Restart auto- 0.9 0,RW/SC negotiation Preliminary Version: DM9601-DS-P01 April 24, ...
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Duplex mode 0.7 Collision test 0.6-0.0 RESERVED 11.2 Basic Mode Status Register (BMSR Bit Bit Name Default 1.15 100BASE-T4 0,RO/P 100BASE-TX 1.14 1,RO/P full duplex 100BASE-TX 1.13 1,RO/P half duplex 10BASE-T 1.12 1,RO/P full duplex 10BASE-T 1.11 ...
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Jabber detect 0,RO/LH Extended 1.0 1,RO/P capability 11.3 PHY ID Identifier Register #1 (PHYID1 The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM9601. The Identifier consists of a concatenation of ...
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Auto-negotiation Advertisement Register(ANAR) – 04 This register contains the advertised abilities of this DM9601 device as they will be transmitted to its link partner during Auto-negotiation. Bit Bit Name 4.15 NP 4.14 ACK 4.13 RF 4.12-4.11 RESERVED 4.10 FCS ...
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Auto-negotiation Link Partner Ability Register (ANLPAR) – 05 This register contains the advertised abilities of the link partner when received during Auto-negotiation. Bit Bit Name 5.15 NP 5.14 ACK 5.13 RF 5.12-5.11 RESERVED 5.10 FCS 5.9 T4 5.8 TX_FDX ...
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Auto-negotiation Expansion Register (ANER)- 06 Bit Bit Name 6.15-6.5 RESERVED 6.4 PDF 0, RO/LH 6.3 LP_NP_ABLE 6.2 NP_ABLE 6.1 PAGE_RX 0, RO/LH 6.0 LP_AN_ABLE 11.8 DAVICOM Specified Configuration Register (DSCR Bit Bit Name 16.15 BP_4B5B 16.14 BP_SCR ...
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RESERVED 16.5 RESERVED 16.4 RPDCTR-EN 16.3 SMRST 16.2 MFPSC 16.1 SLEEP 16.0 RLOUT 11.9 DAVICOM Specified Configuration and Status Register (DSCSR Bit Bit Name 17.15 100FDX 17.14 100HDX 17.13 10FDX 17.12 10HDX Preliminary Version: DM9601-DS-P01 June 22, ...
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RESERVED 17.9 (PHYADR), 17.8-17.4 PHYADR[4:0] 17.3-17.0 ANMB[3:0] 36 USB to Ethernet MAC Controller with Integrated 10/100 PHY If this bit means the operation 1 mode is a 10M half duplex mode. The software can read bit[15:12] ...
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Configuration/Status (10BTCSR Bit Bit Name 18.15 RESERVED 18.14 LP_EN 18.13 HBE 18.12 SQUELCH 18.11 JABEN 12. 18.10- RESERVED 18.1 18.0 POLR Preliminary Version: DM9601-DS-P01 June 22, 2001 USB to Ethernet MAC Controller with Integrated 10/100 PHY ...
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Functional Description 12.1 100Base-TX Operation The block diagram in figure 3 provides an overview of the functional blocks contained in the transmit section. The transmitter section contains the following functional blocks: - 4B5B Encoder - Scrambler - Parallel to ...
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Code Group Symbol Preliminary Version: DM9601-DS-P01 ...
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Receiver The 100Base-TX receiver contains several function blocks that convert the scrambled 125Mb/s serial data to synchronous 4-bit nibble data that is then provided to the MII. The receive section contains the following functional blocks: - Signal Detect ...
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Code Group Alignment The Code Group Alignment block receives un-aligned 5B data from the descrambler and converts it into 5B code group data. Code Group Alignment occurs after the J/K is detected, and subsequent data is aligned on a ...
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Power Reduced Mode The Signal detect circuit is always turned on to monitor the signal if there is no signal on the media (cable disconnected). The DM9601 automatically turns off the power and enters the Power Reduced mode, whether ...
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DC and AC Electrical Characteristics 13.1 Absolute Maximum Ratings ( Symbol D A Supply Voltage Vdd, Vdd V DC Input Voltage ( Output Voltage(V OUT T Storage Temperature Rang (T stg Tc Case ...
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DC Electrical Characteristics Symbol Parameter TTL Inputs (TXD0~TXD3, TXCLK, MDC, MDIO, TXEN, TXER, RXEN, TESTMODE, RMII, PHYAD0~4, OPMODE0-2, RPTR, BP4B5B, RESET# ) VIL Input Low Voltage VIH Input High Voltage IIL Input Low Leakage Current IIH Input High Leakage ...
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AC Electrical Characteristics & Timing Waveforms 13.5.1 TP Interface Symbol Parameter tTR/F 100TX+/- Differential Rise/Fall Time TTM 100TX+/- Differential Rise/Fall Time Mismatch TTDC 100TX+/- Differential Output Duty Cycle Distortion tT/T 100TX+/- Differential Output Peak-to-Peak Jitter XOST 100TX+/- Differential Voltage ...
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Symbol TXEN,TXD[3：0] setup time T1 TXEN,TXD[3：0] hold time T2 13.5.5 External MII Interface Receive Timing RXCK RXER,RXDV → RXD[3:0] Symbol RXER, RXDV,RXD[3：0] setup time T1 T2 RXER, RXDV,RXD[3：0] hold time ← MDC MDIO (drive by DM9601) MDIO (drive by externcl ...
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EEPROM Interface Timing → ← T2 EESS EECK → T4 EEDO EEDI Symbol T1 EECK frequency T2 EECS setup time T3 EECS hold time T4 EEDO setup time T5 EEDO hold time T6 EEDI setup time T7 EEDI hold ...
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Application Notes 14.1 Network Interface Signal Routing Place the transformer as close as possible to the RJ-45 connector. Place all the 50Ω resistors as close as possible to the DM9601 RX± and TX± pins. Traces routed from RX± and ...
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Reduction Application) 29 RX+ 50Ω RX- 50Ω 1% 3.3V AVCC DM9601 78Ω TX+ 78Ω TX- 26 BGRES 25 BGRESG Preliminary Version: DM9601-DS-P01 June 22, 2001 USB to Ethernet MAC Controller with ...
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USB 1.1 Application: DM9601 USB 1.1 Application Layout Guide: for the USB differential signal DP/DM connecting to the USB connector: The traces inhibit crossover on the DP/DM Signal. The termination resistances should be as close as possible to the ...
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Power Decoupling Capacitors Davicom Semiconductor recommends to place all the decoupling capacitors for all power supply pins as close as possible to the power pads of the DM9601 (The best placed distance is < 3mm from the above mentioned ...
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Ground Plane Layout Davicom Semiconductor recommends a single ground plane approach to minimize EMI. Ground plane partitioning can cause increased EMI emissions that could make the 52 USB to Ethernet MAC Controller with Integrated 10/100 PHY network interface card ...
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Power Plane Partitioning The power planes should be approximately illustrated in Figure 6. The ferrite bead used should have an impedance at least 75Ω at 100MHz. A suitable bead is the Panasonic surface mound bead, part number EXCCL4532U or ...
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Magnetics Selection Guide Refer to Table 2 for transformer requirements. Transformers meeting these requirements are available from a variety of magnetic manufacturers. Designers should test and qualify all magnetics before Manufacturer Pulse Engineering Delta YCL Halo Nano Pulse Inc. ...
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Package Information 15.1 LQFP 100L Outline Dimensions 75 76 100 1 e See Detail F Seating Plane Symbol Notes: 1. Dimension D & not include resin fins. 2. Dimension GD is for ...
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... Ordering Information Part Number Pin Count DM9601E 100 Disclaimer The information appearing in this publication is believed to be accurate. Integrated circuits sold by DAVICOM Semiconductor are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. DAVICOM makes no warranty, express, statutory, implied or by ...
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Preliminary Version: DM9601-DS-P01 April 24, 2001 USB to Ethernet MAC controller with Integrated 10/100 PHYsceiver DM9601 57 ...
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Data Sheet Changed Errata List 05/02/2001 P01 DM9601 Data Sheet start 05/31/2001 P01 Modify Page 1 Block Diagram 06/22/2001 P01 Page 20 Before Modification: 4 BKPM 0,RW 3 BKPA 0,RW After modification: 4 BKPA 0,RW 3 BKPM 0,RW 58 USB ...