MM82PC12J NSC [National Semiconductor], MM82PC12J Datasheet - Page 4

• Manufacturer Part Number: MM82PC12J
• Description: 8-Bit Input/Output Port
• Manufacturer: NSC [National Semiconductor]

Figure 1 illustrates the calculations of a more useful propa-
Propagation Delays
gation delay The figure uses a 5V supply with a tolerance of
tance of 100 pF The AC Characteristics table depicts t
at 5V 25 C equalling 25 ns Use the graph in Figure 1 to get
the degradation multiple for 150 pF The number shown is
1 09 The adjusted propagation delay is therefore 25
1 09 or 27 ns
g
Including jig and probe capacitance
FIGURE 1 Normalized Typical Propagation Delay vs
10% ambient temperature of
for Propagation Delays
Output Test Circuit
Load Capacitance
a
25 C and a load capaci-
TL C 5596– 7
TL C 5596– 8
TL C 5596– 9
PD
c
4
Pin Descriptions
The following describes the function of all the MM82PC12
input output pins Some of these descriptions reference in-
ternal circuits
INPUT SIGNALS
Device Select (DS
the device is selected The output buffers are enabled and
the service request flip-flop is asynchronously reset
(cleared) when the device is selected
Mode (MD) When MD is high (output mode) the output
buffers are enabled and the source of the data latch clock
input is the device selection logic (DS
low (input mode) the state of the output buffers is deter-
mined by the device selection logic (DS
source of the data latch clock input is the strobe (STB) in-
put
Strobe (STB) STB is used as the data latch clock input
when the mode (MD) input is low (input mode) STB is also
used to synchronously set the service request flip-flop
which is negative edge triggered
Data In (DI
latch which consists of eight D-type flip-flops incorporating
a level sensitive clock While the data latch clock input is
high the Q output of each flip-flop follows the data input
When the clock input returns low the data latch stores the
data input Clear (CLR) is only effective when the clock is
low (latch in the latched state)
Clear (CLR) When CLR is low the data latch is reset
(cleared) if the clock is also low The clock input high over-
rides the clear (CLR) input data latch reset CLR being low
also resets the service request flip-flop The service request
flip-flop is in the non-interrupting state when reset
OUTPUT SIGNALS
Interrupt (INT) The interrupt pin goes low (interrupting
state) when either the service request flip-flop is synchro-
nously set by the strobe (STB) input or the device is select-
ed
Data Out (DO
data buffers which are TRI-STATE non-inverting stages
These buffers have a common control line that either en-
ables the buffers to transmit the data from the data latch
outputs or disables the buffers by placing them in the high-
impedance state
Reliability Information
Gate Count 108
Transistor Count 248
1
–DI
1
–DO
8
) Data In is the 8-bit data input to the data
1
8
DS
) Data Out is the 8-bit data output of
2
When DS
1
is low and DS
1
DS
1
2
) When MD is
DS
2
) and the
2
is high