93LC56A-I/SM MICROCHIP [Microchip Technology], 93LC56A-I/SM Datasheet - Page 3

• Manufacturer Part Number: 93LC56A-I/SM
• Description: 2K 2.5V Microwave Serial EEPROM
• Manufacturer: MICROCHIP [Microchip Technology]

2.0
2.1
A high level selects the device; a low level deselects the
device and forces it into standby mode. However, a pro-
gramming cycle which is already in progress will be
completed, regardless of the Chip Select (CS) input
signal. If CS is brought low during a program cycle, the
device will go into standby mode as soon as the pro-
gramming cycle is completed.
CS must be low for 250 ns minimum (T
consecutive instructions. If CS is low, the internal con-
trol logic is held in a RESET status.
2.2
The Serial Clock is used to synchronize the communi-
cation between a master device and the 93LC56A/B.
Opcode, address, and data bits are clocked in on the
positive edge of CLK. Data bits are also clocked out on
the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at high or low level) and can be continued
anytime with respect to clock high time (T
clock low time (T
freedom in preparing opcode, address, and data.
CLK is a “Don't Care” if CS is low (device deselected).
If CS is high, but START condition has not been
detected, any number of clock cycles can be received
by the device without changing its status (i.e., waiting
for START condition).
TABLE 2-1
TABLE 2-2
Instruction SB Opcode
Instruction SB Opcode
1997 Microchip Technology Inc.
ERASE
WRITE
ERASE
WRITE
EWDS
EWEN
WRAL
READ
EWDS
EWEN
WRAL
ERAL
READ
ERAL
PIN DESCRIPTION
Chip Select (CS)
Serial Clock (CLK)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CKL
INSTRUCTION SET FOR 93LC56A
INSTRUCTION SET FOR 93LC56B
). This gives the controlling master
11
00
00
00
10
01
00
11
00
00
00
10
01
00
X
X
X
1
0
1
0
X
X
X
1
0
1
0
A7 A6 A5 A4 A3 A2 A1 A0
A7 A6 A5 A4 A3 A2 A1 A0
A7 A6 A5 A4 A3 A2 A1 A0
0
0
1
1
A6
A6
A6
0
0
1
1
X
X
X
X
CSL
A5
A5
A5
X
X
X
X
) between
X
X
X
X
CKH
Address
Address
A4
A4
A4
X
X
X
X
) and
X
X
X
X
Preliminary
A3
A3
A3
X
X
X
X
X
X
X
X
A2
A2
A2
X
X
X
X
X
X
X
X
A1
A1
A1
X
X
X
X
X
X
X
X
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
After detection of a START condition the specified num-
ber of clock cycles (respectively low to high transitions
of CLK) must be provided. These clock cycles are
required to clock in all required opcode, address, and
data bits before an instruction is executed (Table 2-1
and Table 2-2). CLK and DI then become don't care
inputs waiting for a new START condition to be
detected.
2.3
Data In is used to clock in a START bit, opcode,
address, and data synchronously with the CLK input.
2.4
Data Out is used in the READ mode to output data syn-
chronously with the CLK input (T
edge of CLK).
This pin also provides READY/BUSY status information
during ERASE and WRITE cycles. READY/BUSY sta-
tus information is available on the DO pin if CS is
brought high after being low for minimum chip select
low time (T
been initiated.
The status signal is not available on DO, if CS is held
low during the entire ERASE or WRITE cycle. In this
case, DO is in the HIGH-Z mode. If status is checked
after the ERASE/WRITE cycle, the data line will be high
to indicate the device is ready.
A0
A0
A0
X
X
X
X
X
X
X
X
Data In
D15 - D0
D15 - D0
D7 - D0
D7 - D0
Data In
Data In (DI)
Data Out (DO)
—
—
—
—
—
CSL
—
—
—
—
—
) and an ERASE or WRITE operation has
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
Data Out
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
Data Out
D15 - D0
HIGH-Z
HIGH-Z
D7 - D0
HIGH-Z
HIGH-Z
93LC56A/B
PD
Req. CLK Cycles
Req. CLK Cycles
after the positive
DS21208A-page 3
12
12
12
12
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20
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11
11
11
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