34LC02 MICROCHIP [Microchip Technology], 34LC02 Datasheet - Page 7

• Manufacturer Part Number: 34LC02
• Manufacturer: MICROCHIP [Microchip Technology]

FIGURE 3-1:
3.6
A control byte is the first byte received following the
Start condition from the master device. The first part of
the control byte consists of a 4-bit control code which is
set to ‘1010’ for normal read and write operations and
‘0110’ for writing to the write-protect register. The
control byte is followed by three Chip Select bits (A2,
A1, A0). The Chip Select bits allow the use of up to
eight 34XX02 devices on the same bus and are used to
determine which device is accessed. The Chip Select
bits in the control byte must correspond to the logic lev-
els on the corresponding A2, A1 and A0 pins for the
device to respond.
The eighth bit of slave address determines if the master
device wants to read or write to the 34XX02
(Figure 3-2). When set to a one, a read operation is
selected. When set to a zero, a write operation is
selected.
FIGURE 3-2:
 2010 Microchip Technology Inc.
Read
Write
Write-Protect Register
SDA
SCL
Start
Operation
1
0
(A)
Device Addressing
0
1
Condition
Slave Address
1
1
Start
(B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
CONTROL BYTE
ALLOCATION
OR
0
0
Control
Code
1010
1010
0110
A2
A2
Read/Write
A1
A1
A2 A1 A0
A2 A1 A0
A2 A1 A0
Select
Chip
Acknowledge
A0
A0
Address or
R/W A
Valid
(D)
R/W
1
0
0
to Change
Allowed
Data
4.0
4.1
Following the Start signal from the master, the device
code(4 bits), the Chip Select bits (3 bits) and the R/W
bit, which is a logic low, are placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow,
once it has generated an Acknowledge bit during the
ninth clock cycle. Therefore, the next byte transmitted
by the master is the word address and will be written
into the Address Pointer of the 34XX02.
After receiving another Acknowledge signal from the
34XX02, the master device will transmit the data word
to be written into the addressed memory location. The
34XX02 acknowledges again and the master generates
a Stop condition. This initiates the internal write cycle,
which means that during this time, the 34XX02 will not
generate Acknowledge signals (Figure 4-1). If an
attempt is made to write to the array when the software
or hardware write protection has been enabled, the
device will acknowledge the command, but no data will
be written. The write cycle time must be observed even
if the write protection is enabled.
4.2
The write control byte, word address and the first data
byte are transmitted to the 34XX02 in the same way as
in a byte write. Instead of generating a Stop condition,
the master transmits up to 15 additional data bytes to
the 34XX02, which are temporarily stored in the on-
chip page buffer and will be written into the memory
after the master has transmitted a Stop condition. Upon
receipt of each word, the four lower order Address
Pointer bits are internally incremented by one. The
higher order four bits of the word address remain
constant. If the master should transmit more than 16
bytes prior to generating the Stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the Stop condition is received, an
WRITE OPERATIONS
Byte Write
Page Write
34AA02/34LC02
(D)
DS22029E-page 7
Condition
Stop
(C)
(A)