M24128-BN5T STMICROELECTRONICS [STMicroelectronics], M24128-BN5T Datasheet - Page 4

• Manufacturer Part Number: M24128-BN5T
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M24256, M24128
Figure 4. I
must be stable during the clock low-to-high transi-
tion, and the data must change only when the SCL
line is low.
Memory Addressing
To start communication between the bus master
and the slave memory, the master must initiate a
START condition. Following this, the master sends
the 8-bit byte, shown in Table 3, on the SDA bus
line (most significant bit first). This consists of the
7-bit Device Select Code, and the 1-bit Read/Write
Designator (RW). The Device Select Code is fur-
Table 3. Device Select Code
Note: 1. The most significant bit, b7, is sent first.
4/17
Device Select Code
SCL
SDA
SCL
SDA
SCL
SDA
2
C Bus Protocol
Condition
START
b7
1
MSB
Condition
START
1
MSB
Device Type Identifier
1
1
b6
0
2
2
Input
SDA
3
b5
1
3
Change
SDA
ther subdivided into: a 4-bit Device Type Identifier,
and a 3-bit Chip Enable “Address” (0, 0, 0).
To address the memory array, the 4-bit Device
Type Identifier is 1010b.
The 8
and ‘0’ for write operations. If a match occurs on
the Device Select Code, the corresponding mem-
ory gives an acknowledgment on the SDA bus dur-
ing the 9
the Device Select Code, it deselects itself from the
bus, and goes into stand-by mode.
b4
0
th
7
bit is the RW bit. This is set to ‘1’ for read
th
7
bit time. If the memory does not match
b3
0
8
Chip Enable
8
b2
ACK
0
9
Condition
ACK
STOP
9
Condition
STOP
b1
0
RW
RW
AI00792B
b0