W9751G6KB WINBOND [Winbond], W9751G6KB Datasheet - Page 7

• Manufacturer Part Number: W9751G6KB
• Description: 8M ? 4 BANKS ? 16 BIT DDR2 SDRAM
• Manufacturer: WINBOND [Winbond]

5. BALL DESCRIPTION
M8,M3,M7,N2,N8,N3
,N7,P2,P8,P3,M2,P7
,R2
,F1,F9,C8,C2,D7,D3,
A9,C1,C3,C7,C9,E9,
G1,G3,G7,G9
A7,B2,B8,D2,D8,E7,
F2,F8,H2,H8
G8,G2,H7,H3,H1,H9
A2,E2,L1,R3,R7,R8
BALL NUMBER
A1,E1,J9,M9,R1
A3,E3,J3,N1,P9
D1,D9,B1,B9
K7,L7,K3
F7,E8
B7,A8
B3,F3
J8,K8
L2,L3
K9
L8
K2
J2
J7
J1
UDQS, UDQS
LDQS, LDQS LOW Data Strobe
RAS , CAS ,
DQ0−DQ15
CLK, CLK
UDM, LDM
SYMBOL
BA0−BA1
A0−A12
V
V
V
V
V
ODT
CKE
V
V
WE
CS
SSDL
NC
DDQ
SSQ
REF
DDL
DD
SS
Reference Voltage V
DLL Power Supply DLL Power Supply: 1.8V  0.1V.
DQ Power Supply DQ Power Supply: 1.8V  0.1V.
Command Inputs
Differential Clock
Input Data Mask
UP Data Strobe
No Connection
Power Supply
Clock Enable
FUNCTION
DLL Ground
Bank Select
Termination
Chip Select
DQ Ground
Data Input
Address
/ Output
Ground
Control
On Die
Inputs
Provide the row address for active commands, and the column address
and Auto-precharge bit for Read/Write commands to select one
location out of the memory array in the respective bank.
Row address: A0−A12.
Column address: A0−A9. (A10 is used for Auto-precharge)
BA0−BA1 define to which bank an ACTIVE, READ, WRITE or
PRECHARGE command is being applied.
Bi-directional data bus.
ODT (registered HIGH) enables termination resistance internal to the
DDR2 SDRAM.
Data Strobe for Lower Byte: Output with read data, input with write data
for source synchronous operation. Edge-aligned with read data, center-
aligned with write data. LDQS corresponds to the data on DQ0−DQ7.
the control bit at EMR (1)[A10 EMRS command].
Data Strobe for Upper Byte: Output with read data, input with write data
for source synchronous operation. Edge-aligned with read data, center-
aligned with write data. UDQS corresponds to the data on DQ8−DQ15.
the control bit at EMR (1)[A10 EMRS command].
All commands are masked when CS is registered HIGH
for external bank selection on systems with multiple ranks. CS is
considered part of the command code.
entered.
DM is an input mask signal for write data. Input data is masked when
DM is sampled high coincident with that input data during a Write
access. DM is sampled on both edges of DQS. Although DM pins are
input only, the DM loading matches the DQ and DQS loading.
CLK and CLK are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of CLK
and negative edge of CLK . Output (read) data is referenced to the
crossings of CLK and CLK (both directions of crossing).
CKE (registered HIGH) activates and CKE (registered LOW)
deactivates clocking circuitry on the DDR2 SDRAM.
Power Supply: 1.8V  0.1V.
Ground.
DQ Ground. Isolated on the device for improved noise immunity.
No connection.
DLL Ground.
LDQS is only used when differential data strobe mode is enabled via
UDQS is only used when differential data strobe mode is enabled via
RAS , CAS and WE (along with CS ) define the command being
REF
- 7 -
is reference voltage for inputs.
Publication Release Date: Dec. 09, 2011
DESCRIPTION
W9751G6KB
Revision A01
.
CS provides