LH28F160S5-L SHARP [Sharp Electrionic Components], LH28F160S5-L Datasheet - Page 22

• Manufacturer Part Number: LH28F160S5-L
• Description: 16 M-bit (2 MB x 8/1 MB x 16) Smart 5 Flash Memories (Fast Programming)
• Manufacturer: SHARP [Sharp Electrionic Components]

protected against alteration. A successful clear
block lock-bits operation requires WP# = V
attempted with WP# = V
set to "1" and the operation will fail. Clear block
lock-bits operation with V
results and should not be attempted.
If a clear block lock-bits operation is aborted due to
V
active transition, block lock-bit values are left in an
undetermined state. A repeat of clear block lock-bits
is required to initialize block lock-bit contents to
known values.
4.14 STS Configuration Command
The Status (STS) pin can be configured to different
states using the STS Configuration command.
Once the STS pin has been configured, it remains
in that configuration until another configuration
command is issued, the device is powered down or
RP# is set to V
after exit from deep power-down mode, the STS
pin defaults to RY/BY# operation where STS low
indicates that the WSM is busy. STS High Z
indicates that the WSM is ready for a new
operation.
To reconfigure the STS pin to other modes, the
STS Configuration is issued followed by the
appropriate configuration code. The three alternate
Block Erase or
(Multi) Word/Byte
Write
Full Chip Erase
Set Block Lock-Bit
Clear Block Lock-Bits
PP
OPERATION
or V
CC
transition out of valid range or RP#
IL
. Upon initial device power-up and
LOCK-BIT
BLOCK
IH
0, 1
IL
X
X
X
0
1
, SR.1 and SR.5 will be
< RP# produce spurious
V
IL
Table 12 Write Protection Alternatives
WP#
V
V
V
V
V
V
V
V
or V
IH
IH
IH
IH
IL
IL
IL
IL
IH
IH
Block Erase and (Multi) Word/Byte Write Enabled
Block is Locked. Block Erase and (Multi) Word/Byte Write Disabled
Block Lock-Bit Override. Block Erase and (Multi) Word/Byte Write Enabled
All unlocked blocks are erased, locked blocks are not erased
All blocks are erased
Set Block Lock-Bit Disabled
Set Block Lock-Bit Enabled
Clear Block Lock-Bits Disabled
Clear Block Lock-Bits Enabled
. If it is
- 22 -
configurations are all pulse mode for use as a
system interrupt. The STS Configuration command
functions independently of the V
RP# must be V
CONFIGURATION
Table 11 STS Configuration Coding Description
01H
02H
03H
BITS
00H
EFFECT
Set STS pin to default level mode
(RY/BY#). RY/BY# in the default
level-mode of operation will indicate
WSM status condition.
Set STS pin to pulsed output signal
for specific erase operation. In this
mode, STS provides low pulse at the
completion of Block Erase, Full Chip
Erase and Clear Block Lock-Bits
operations.
Set STS pin to pulsed output signal
for a specific write operation. In this
mode, STS provides low pulse at the
completion of (Multi) Byte Write and
Set Block Lock-Bit operation.
Set STS pin to pulsed output signal
for specific write and erase operation.
STS provides low pulse at the
completion of Block Erase, Full Chip
Erase, (Multi) Word/Byte Write and
Block Lock-Bit Configuration operations.
IH
.
LH28F160S5-L/S5H-L
EFFECTS
PP
voltage and