W9812G6GH-6 WINBOND [Winbond], W9812G6GH-6 Datasheet - Page 37

• Manufacturer Part Number: W9812G6GH-6
• Description: 2M X 4 BANKS X 16 BITS SDRAM
• Manufacturer: WINBOND [Winbond]

11.17
11.18 Timing Chart of Write to Read Cycle
Timing Chart of Read to Write Cycle
In the case of Burst Length = 4
(1) CAS Latency=2
(1) CAS Latency=2
(2) CAS Latency=3
(2) CAS Latency=3
( a ) Command
( a ) Command
( b ) Command
( b ) Command
( a ) Command
( b ) Command
( a ) Command
( b ) Command
DQM
DQM
DQM
DQM
DQ
In the case of Burst Length=4
DQ
DQ
DQ
DQM
DQM
DQM
DQM
DQ
DQ
DQ
DQ
0
0
Write
Write
Write
Write
Read
Read Write
Read
Read
D0
D0
D0
1
D0
1
Note: The Output data must be masked by DQM to avoid I/O conflict
Read
Read
Write
D1
D1
D0
2
2
D0
Read
Write
Read
Write
- 37
D1
D0
D1
D0
3
3
D2
D1
D1
Q0
D2
4
4
D3
D2
D2
D3
Q1
Q0
Q0
5
5
D3
D3
Q2
Q1
Q1
Q0
6
6
Q3
Q2
Q1
Q2
7
7
Publication Release Date:Aug. 13, 2007
Q2
Q3
Q3
8
8
Q3
9
9
W9812G6GH
10
10
11
11
-Revision A06