IS41C44002 ICSI [Integrated Circuit Solution Inc], IS41C44002 Datasheet - Page 4

• Manufacturer Part Number: IS41C44002
• Description: 4Mx4 bit Dynamic RAM with EDO Page Mode
• Manufacturer: ICSI [Integrated Circuit Solution Inc]

IC41C4400x and IC41LV4400x Series
Functional Description
The IC41C4400x and IC41LV4400x are CMOS DRAMs
optimized for high-speed bandwidth, low power
applications. During READ or WRITE cycles, each bit is
uniquely addressed through the 11 or 12 address bits.
These are entered 11 bits (A0-A10) at a time for the 2K
refresh device or 12 bits (A0-A11) at a time for the 4K
refresh device. The row address is latched by the Row
Address Strobe (RAS). The column address is latched by
the Column Address Strobe (CAS). RAS is used to latch
the first nine bits and CAS is used the latter ten bits.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum t
cycle must not be initiated until the minimum precharge
time t
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The
column address must be held for a minimum time specified
by t
and t
dependent on the timing relationships between these
parameters.
Write Cycle
A write cycle is initiated by the falling edge of CAS and WE,
whichever occurs last. The input data must be valid at or
before the falling edge of CAS or WE, whichever occurs
last.
4
AR
OEA
RP
. Data Out becomes valid only when t
, t
are all satisfied. As a result, the access time is
CP
has elapsed.
RAS
time has expired. A new
RAC
, t
AA
, t
CAC
Refresh Cycle
To retain data, 2,048 refresh cycles are required in each
32 ms period, or 4,096 refresh cycles are required in each
64ms period. There are two ways to refresh the memory:
1. By clocking each of the 2,048 row addresses (A0
2. Using a CAS-before-RAS refresh cycle. CAS-before-
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Power-On
After application of the V
200 µs is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a
RAS signal).
During power-on, it is recommended that RAS track with
V
CC
through A10) or 4096 row addresses (A0 through A11)
with RAS at least once every 32 ms or 64ms respectively.
Any read, write, read-modify-write or RAS-only cycle
refreshes the addressed row.
RAS refresh is activated by the falling edge of RAS,
while holding CAS LOW. In CAS-before-RAS refresh
cycle, an internal 9-bit counter provides the row ad-
dresses and the external address inputs are ignored.
or be held at a valid V
Integrated Circuit Solution Inc.
CC
IH
to avoid current surges.
supply, an initial pause of
DR007-0B 10/17/2002