STK12C68-CF25 SIMTEK [Simtek Corporation], STK12C68-CF25 Datasheet - Page 9

• Manufacturer Part Number: STK12C68-CF25
• Description: 8Kx8 AutoStore nvSRAM
• Manufacturer: SIMTEK [Simtek Corporation]

Document Control #ML0008 Rev 0.7
The STK12C68 has two separate modes of opera-
tion:
mode, the memory operates as a standard fast static
RAM
SRAM
tion) or from Nonvolatile Elements to
RECALL
disabled.
NOISE CONSIDERATIONS
The STK12C68 is a high-speed memory and so
must have a high-frequency bypass capacitor of
approximately 0.1μF connected between V
V
sible. As with all high-speed
ful routing of power, ground and signals will help
prevent noise problems.
SRAM READ
The STK12C68 performs a
and G are low and W and HSB are high. The
address specified on pins A
the 8,192 data bytes will be accessed. When the
READ
puts will be valid after a delay of t
#1). If the
be valid at t
cycle #2). The data outputs will repeatedly respond to
address changes within the t
the need for transitions on any control input pins, and
will remain valid until another address change or until
E or G is brought high, or W or HSB is brought low.
SRAM WRITE
A
low and HSB is high. The address inputs must be
stable prior to entering the
remain stable until either E or W goes high at the
end of the cycle. The data on the common I/O pins
DQ
before the end of a W controlled
before the end of an E controlled
It is recommended that G be kept high during the
entire
common I/O lines. If G is left low, internal circuitry
will turn off the output buffers t
SS
WRITE
, using leads and traces that are as short as pos-
0-7
. In nonvolatile mode, data is transferred from
February 2007
SRAM
will be written into the memory if it is valid t
is initiated by an address transition, the out-
WRITE
to Nonvolatile Elements (the
operation). In this mode
cycle is performed whenever E and W are
READ
ELQV
mode and nonvolatile mode. In
cycle to avoid data bus contention on
is initiated by E or G, the outputs will
or at t
GLQV
, whichever is later (
READ
CMOS
0-12
AVQV
WRITE
WLQZ
determines which of
access time without
SRAM
WRITE
cycle whenever E
after W goes low.
ICs, normal care-
AVQV
cycle and must
WRITE
DEVICE OPERATION
STORE
functions are
(
.
READ
SRAM
CAP
or t
opera-
SRAM
READ
cycle
DVWH
(the
and
DVEH
9
POWER-UP RECALL
During power up, or after any low-power condition
(V
latched. When V
voltage of V
be initiated and will take t
If the STK12C68 is in a
power-up
To help avoid this situation, a 10K Ohm resistor
should be connected either between W and system
V
SOFTWARE NONVOLATILE STORE
The STK12C68 software
executing sequential
six specific address locations. During the
cycle an erase of the previous nonvolatile data is
first performed, followed by a program of the nonvol-
atile elements. The program operation copies the
SRAM
cycle is initiated, further input and output are dis-
abled until the cycle is completed.
Because a sequence of
addresses is used for
that no other
the sequence, or the sequence will be aborted and
no
To initiate the software
READ
The software sequence must be clocked with E con-
trolled
Once the sixth address in the sequence has been
entered, the
chip will be disabled. It is important that
and not
although it is not necessary that G be low for the
sequence to be valid. After the t
been fulfilled, the
READ
CC
CAP
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
STORE
or between E and system V
< V
sequence must be performed:
and
data into nonvolatile memory. Once a
READ
STK12C68 (SMD5962-94599)
WRITE
RESET
RECALL
or
WRITE
SWITCH
s.
RECALL
STORE
READ
), an internal
CAP
cycles be used in the sequence,
, a
operation.
, the
SRAM
or
0000 (hex)
1555 (hex)
0AAA (hex)
1FFF (hex)
10F0 (hex)
0F0F (hex)
once again exceeds the sense
RECALL
E
cycle will commence and the
will take place.
STORE
WRITE
SRAM
controlled
STORE
RESTORE
STORE
will again be activated for
WRITE
RECALL
cycle will automatically
initiation, it is important
READ
data will be corrupted.
accesses intervene in
CC
to complete.
cycle, the following
STORE
state at the end of
cycle is initiated by
.
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate STORE cycle
READ
s from specific
request will be
cycle time has
READ
cycles from
STORE
STORE
cycles