STK14D88_08 SIMTEK [Simtek Corporation], STK14D88_08 Datasheet - Page 12

• Manufacturer Part Number: STK14D88_08
• Description: 32Kx8 Autostore nvSRAM
• Manufacturer: SIMTEK [Simtek Corporation]

STK14D88
Document Control #ML0033 Rev 2.0
has taken place. The HSB signal can be monitored
by the system to detect an AutoStore cycle is in
progress.
HARDWARE STORE (HSB) OPERATION
The STK14D88 provides the HSB pin for controlling
and acknowledging the STORE operations. The
HSB pin can be used to request a hardware STORE
cycle. When the HSB pin is driven low, the
STK14D88 will conditionally initiate a STORE oper-
ation after t
begin if a WRITE to the SRAM took place since the
last STORE or RECALL cycle. The HSB pin has a
very resistive pullup and is internally driven low to
indicate a busy condition while the STORE (initiated
by any means) is in progress. This pin should be
externally pulled up if it is used to drive other inputs.
SRAM READ and WRITE operations that are in
progress when HSB is driven low by any means are
given time to complete before the STORE operation
is initiated. After HSB goes low, the STK14D88 will
continue SRAM operations for t
multiple SRAM READ operations may take place. If
a WRITE is in progress when HSB is pulled low, it
will be allowed a time, t
any SRAM WRITE cycles requested after HSB goes
low will be inhibited until HSB returns high.
If HSB is not used, it should be left unconnected.
HARDWARE RECALL (POWER-UP)
During power up or after any low-power condition
(V
latched. When V
voltage of V
cally be initiated and will take t
SOFTWARE STORE
Data can be transferred from the SRAM to the non-
volatile memory by a software address sequence.
The STK14D88 software STORE cycle is initiated
by executing sequential E controlled READ cycles
from six specific address locations in exact order.
During the STORE cycle, previous data is erased
and then the new data is programmed into the non-
volatile elements. Once a STORE cycle is initiated,
further memory inputs and outputs are disabled until
the cycle is completed.
CC
<V
Jan 2008
SWITCH
DELAY
SWITCH
), an internal RECALL request will be
CC
. An actual STORE cycle will only
, a RECALL cycle will automati-
once again exceeds the sense
DELAY
, to complete. However,
HRECALL
DELAY
. During t
to complete.
DELAY
12
,
To initiate the software STORE cycle, the following
READ sequence must be performed:
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that READ
cycles and not WRITE cycles be used in the
sequence. After the t
filled, the SRAM will again be activated for READ
and WRITE operation.
SOFTWARE RECALL
Data can be transferred from the nonvolatile mem-
ory to the SRAM by a software address sequence. A
software RECALL cycle is initiated with a sequence
of READ operations in a manner similar to the soft-
ware STORE initiation. To initiate the RECALL
cycle, the following sequence of E controlled READ
operations must be performed:
Internally, RECALL is a two-step procedure. First,
the SRAM data is cleared, and second, the nonvola-
tile information is transferred into the SRAM cells.
After the t
again be ready for READ or WRITE operations. The
RECALL operation in no way alters the data in the
nonvolatile storage elements.
1 Read A ddress 0x0E38 V alid REA D
2 Read A ddress 0x31C7 V alid REA D
3 Read A ddress 0x03E0 V alid REA D
4 Read A ddress 0x3C1F V alid REA D
5 Read A ddress 0x303F V alid REA D
6 Read A ddress 0x0FC0 Initiate STORE Cycle
1 Read A ddress 0x0E38 V alid REA D
2 Read A ddress 0x31C7 V alid REA D
3 Read A ddress 0x03E0 V alid REA D
4 Read A ddress 0x3C1F V alid REA D
5 Read A ddress 0x303F V alid REA D
6 Read A ddress 0x0C63 Initiate RECA LL Cycle
RECALL
cycle time, the SRAM will once
STORE
cycle time has been ful-