BCRT-ACA ETC1 [List of Unclassifed Manufacturers], BCRT-ACA Datasheet - Page 5

• Manufacturer Part Number: BCRT-ACA
• Description: BCRT Bus Controller/Remote Terminal/Monitor
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

The 8-bit write-only Control Register manages the operation of the RTI. Write to the Control Register by applying a logic zero
to CS, CTRL, RD/WR, and ADDR IN (0); if ADDR IN (0) is a logic one a master reset occurs. Data is loaded into the Control
Register via I/O pins DATA(7:0). Control Register writes must occur 50ns before the rising edge of COMSTR to latch data in
the outgoing status word.
System Register (Read Only)
The 16-bit read-only System Register provides the RTI system status. Read the System Register by applying a logic zero to
CS, CTRL, ADDR IN (0), and a logic one to RD/WR. The 16-bit contents of the System Register are read from data I/O pins
DATA(15:0).
Bit
Number
0
1
2
3
4
5
6
7
Bit
Number
0
1
2
3
4
5
6
CONTROL REGISTER (WRITE ONLY)
MSB
[ ] defines reset state
X
X
X
Condition
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
Initial
X
Initial
Condition
[0]
[0]
[0]
[0]
[0]
[0]
[1]
X
X
Description
Channel A Enable. A logic one enables Channel A biphase inputs.
Channel B Enable. A logic one enables Channel B biphase inputs.
Terminal Flag. A logic one sets the Terminal Flag bit of the Status Register.
System Busy. A logic one sets the Busy bit of the System Register and inhibits
RTI access to memory. No data words are retrieved or stored; command word is
stored.
Subsystem Busy. A logic one sets the Subsystem Flag bit of the Status Register.
Self-Test Channel Select. This bit selects which channel the internal self-test
checks; a logic one selects Channel A and a logic zero selects Channel B.
Self-Test Enable. A logic one sets the RTI in the internal self-test mode and inhib-
its normal operation. Internal testing is not visible on biphase output
channels.
Service Request. A logic one sets the Service Request bit of the Status Register.
Figure 4. Control Register
X
Description
MCSA(0). The LSB of the mode code or subaddress as indicated by the
logic state of bit 5.
MCSA(1). Mode code or subaddress as indicated by the state of bit 5.
MCSA(2). Mode code or subaddress as indicated by the state of bit 5.
MCSA(3). Mode code or subaddress as indicated by the state of bit 5.
MCSA(4). Mode code or subaddress as indicated by the state of bit 5.
MC/SA. A logic one indicates that bits 4 through 0 are the subaddress of
the last command word, and that the last command word was a normal
transmit orreceive command. A logic zero indicates that bits 4 through 0
are a mode code, and that the last command was a mode code.
Channel A/B. A logic one indicates that the most recent command arrived
onChannel A; a logic zero indicates that it arrived on Channel B.
X
SRV
[0]
RQ
SELF
TEST
[0]
SELF
[0]
CH
SUBS
[0]
BUSY
[0]
[0]
TF
CH B
[0]
EN
CH A
RTI-5
LSB
[0]
EN