LM5050MK-2 NSC [National Semiconductor], LM5050MK-2 Datasheet - Page 2

• Manufacturer Part Number: LM5050MK-2
• Description: EVAL Evaluation Board Minimum Input Voltage, 6V
• Manufacturer: NSC [National Semiconductor]

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Inductive Kick-Back Protection
Diode D1 and capacitor C1 serve as inductive kick-back pro-
tection to limit negative transient voltage spikes generated on
the input when the input supply voltage is abruptly taken to
zero volts.
Diode D2 and capacitor C2 serve as inductive kick-back pro-
tection to limit positive transient voltage spikes generated on
the output when the input supply voltage is abruptly taken to
zero volts.
Off Test Point
The Off test point provided on the LM5050-2 evaluation board
is used to control the LM5050-2 operation. The Off test point
is connected directly to the LM5050-2 OFF pin. See the
LM5050 datasheet for more details.
To enable the LM5050-2 apply a voltage less than 0.8V to the
Off test point, connect the Off test point to GND, or leave the
Off test point open (default). If the Off test point is left open,
the LM5050-2 OFF pin internal pull-down will ensure that the
LM5050-2 becomes operational.
To disable the LM5050-2 apply a voltage greater than 2.0V to
the Off test point.
V
An external voltage is applied to the V
the logical output of the Status test point can be evaluated.
The V
through a 10 kΩ pull-up resistor. The voltage applied to the
V
Status (nPGD) Test Point
The nPGD test point is wired directly to the LM5050-2 open-
drain nFGD pin (device pin 1), with pull-up bias from the
V
While the Off test point is low, or open, the nFGD pin will be
in a high impedance state and the nPGD test point voltage
will be at a logic high.
When the Off test point is high, the MOSFET Gate drive is
OFF. If the MOSFET is normal, current will begin flowing
LOGIC
LOGIC
LOGIC
LOGIC
test point should be between 3.0V and 5.5V.
test point through a 10 kΩ pull-up resistor.
Test Point
pin is connected to the LM5050-2 nFGD pin
LOGIC
test point so that
2
through the body diode and the voltage difference between
the IN pin and the OUT pin will be greater than the V
threshold of typically 350 mV. In this case the nFGD pin will
go to a low impedance stage and the nPGD test point voltage
will be at a logic low..
If the MOSFET is shorted, the voltage difference between the
IN pin and the OUT pin will be less than the V
of typically 350 mV. In this case the nFGD pin will remain in
a high impedance state and the nPGD test point voltage will
remain at a logic high.
There are several factors that may prevent the nFGD pin from
going to a logic low in an otherwise good application. If there
is a redundant, parallel, supply in operation, that supply may
hold the OUT pin voltage close enough to the IN pin voltage
that the V
high output capacitance value, or a low load current, may re-
quire that a significant amount of time be allowed for the
output capacitance to discharge to the point where the V
(TST)
threshold is exceeded and the nFGD pin goes low.
DS(TST)
FIGURE 3. MOSFET Test, No Fault
threshold is not exceeded. Additionally, a
DS(TST)
30121316
threshold
DS(TST)
DS