LM5069_10 NSC [National Semiconductor], LM5069_10 Datasheet - Page 4
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LM5069_10
Manufacturer Part Number
LM5069_10
Description
Output Voltage Clamping Using the LM5069 Hot Swap Controller
Manufacturer
NSC [National Semiconductor]
Datasheet
1.LM5069_10.pdf
(8 pages)
www.national.com
Referring to Figure 4, initially V
the GATE pin is at approximately 17.6V. The voltage at the
TIMER pin is at zero since the load current is below the cur-
rent limit threshold. When V
20V, there is a momentary current surge through R
to the capacitor at V
reached the Circuit Breaker limit of the LM5069, which trig-
gered the strong pull-down at the GATE pin.* This is why the
GATE pin voltage quickly dropped almost 10V when V
creased, and the voltage at V
the load current was momentarily reduced. Immediately after
that, the circuit breaker function is shut off (due to the reduced
current level), and the current limit feature of the LM5069 then
limits the current through R
rent limiting (approximately 3 ms in Figure 4) the voltage at
the TIMER pin increases since current limiting is a fault con-
dition.
As the voltage at V
increases with it until it reaches the clamp voltage set by Z1
(19.91V in Figure 4). At this point the voltage at V
Transient testing was performed by quickly increasing V
from 48V to 60V for 20 milliseconds, and then returning V
OUT
OUT
increases the voltage at the GATE pin
(C
S
L
IN
). The current surge amplitude
and Q1. During this time of cur-
OUT
increases quickly from 10V to
IN
dropped a small amount as
and V
OUT
are at 10V, and
S
and Q1
FIGURE 5. Z1 = 56V
OUT
IN
in-
is
IN
IN
4
clamped at 15.55V, and remains at that level for the remaining
time that V
the load current (0.389A) is below the current limit threshold,
and the power dissipated in Q1 (1.73W) is below the power
limit threshold. The TIMER pin voltage is decreasing back to-
wards zero volts. When the voltage at V
the voltage levels at the GATE pin and at V
to their original levels.
*The current surge amplitude was verified with a current
probe in series with R
B) In the second test, a 56V zener diode was used for Z1. The
circuit’s load resistance was 140 ohms, resistive. The result,
shown in Figure 5, is that the GATE pin was clamped at ap-
proximately 56V for V
clamped at between 51V and 51.5V as V
from 52V to 62V. In this test circuit, increasing V
activated the power limiting feature of the LM5069, and Q1
was shut off after the fault timeout period.
to 48V. The load was 240 ohms, resistive, for this test. The
scope photo in Figure 6 shows the results:
IN
is at 20V. During the time that V
30119210
S
IN
.
>44V, and the output voltage was
IN
drops back to 10V,
IN
OUT
OUT
was increased
IN
reduce back
is clamped,
above 62V