A3949_04 ALLEGRO [Allegro MicroSystems], A3949_04 Datasheet
A3949_04
Related parts for A3949_04
A3949_04 Summary of contents
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A3949SLB SOIC N/C 1 MODE 2 PHASE 3 GND 4 SLEEP 5 ENABLE 6 Scale 1:1 OUTA 7 SENSE 8 A3949SLP TSSOP N/C 1 MODE 2 PHASE 3 GND 4 SLEEP 5 ENABLE 6 Scale 1:1 OUTA 7 SENSE 8 ...
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Functional Block Diagram .22 μ VREG Low Side Gate Supply MODE PHASE Control Logic ENABLE SLEEP Control Logic Table PHASE ENABLE MODE SLEEP ...
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ELECTRICAL CHARACTERISTICS Characteristics Symbol Output-On Resistance R DSON Body Diode Forward Voltage V Motor Supply Current Logic Input Voltage IN(1) PHASE, ENABLE, MODE V IN(0) V Logic Input Voltage IN(1) SLEEP V IN(0) I Logic Input Current ...
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PWM Control Timing Diagram SLEEP ENABLE PHASE MODE V BB OUTA OUTB OUT A VBB OUTA DMOS Full-Bridge Motor Driver OUTA OUTB 5 ...
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VREG. This supply voltage is used to operate the sink- side DMOS outputs. VREG is internally monitored and in the case of a fault condition, the outputs of the device are disabled. The VREG pin should be decoupled with a ...
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Terminal List Table Name Description N/C Not used MODE Logic input PHASE Logic input for direction control GND Ground SLEEP Logic input ENABLE Logic input OUTA Output A for full bridge SENSE Power return VBB Load supply voltage OUTB Output ...
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A3949SLB 16-Pin Batwing SOIC .406 .398 16 .299 7.59 .291 7.39 .414 10.52 .398 10. .020 0.51 .014 0.36 .050 1.27 BSC .026 0.66 REF Dimensions in inches Metric dimensions (mm) in brackets, for reference only Leads 4 ...
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DMOS Full-Bridge Motor Driver The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec ...