BH616UV8011_08 BSI [Brilliance Semiconductor], BH616UV8011_08 Datasheet - Page 4
![no-image](/images/no-image-200.jpg)
BH616UV8011_08
Manufacturer Part Number
BH616UV8011_08
Description
Ultra Low Power/High Speed CMOS SRAM 512K X 16 bit
Manufacturer
BSI [Brilliance Semiconductor]
Datasheet
1.BH616UV8011_08.pdf
(11 pages)
R0201-BH616UV8011
Output
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing
Reference Level
Output Load
DATA RETENTION CHARACTERISTICS (T
1. Typical characteristics are at T
2. t
LOW V
LOW V
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
1. Including jig and scope capacitance.
SYMBOL
RC
I
= Read Cycle Time.
t
V
CCDR
V
CE2
CDR
t
DR
CC
R
CC
CC
V
CE1
CC
C
DATA RETENTION WAVEFORM (1) (CE1 Controlled)
DATA RETENTION WAVEFORM (2) (CE2 Controlled)
L
1 TTL
(1)
t
t
Others
CLZ1
CHZ2
V
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
CC
, t
, t
CLZ2
BDO
for Data Retention
PARAMETER
, t
, t
OHZ
BE
GND
, t
V
, t
CC
OLZ
WHZ
A
=25
, t
, t
CHZ1
OW
O
C and not 100% tested.
Rise Time:
1V/ns
10%
,
→ ←
ALL INPUT PULSES
V
1V/ns
0.5Vcc
C
C
CC
L
L
V
= 5pF+1TTL
= 30pF+1TTL
CE1≧V
V
CE1≧V
V
See Retention Waveform
IL
/ 0V
t
90%
IN
IN
V
CDR
≧V
≧V
IH
V
t
CDR
V
CC
CC
CC
CC
90%
CC
CC
-0.2V or V
-0.2V or V
A
TEST CONDITIONS
-0.2V or CE2≦0.2V,
-0.2V or CE2≦0.2V,
Fall Time:
1V/ns
→
= -40
←
10%
Data Retention Mode
O
IN
IN
C to +85
Data Retention Mode
4
≦0.2V
≦0.2V
CE2≦0.2V
CE1≧V
V
DR
V
≧1.0V
DR
≧1.0V
KEY TO SWITCHING WAVEFORMS
CC
WAVEFORM
O
- 0.2V
C)
V
CC
=1.2V
V
MIN.
CC
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM “H” TO “L”
MAY CHANGE
FROM “L” TO “H”
DON’T CARE
ANY CHANGE
PERMITTED
DOES NOT
APPLY
t
RC
1.0
--
t
0
V
R
(2)
CC
V
t
R
IL
V
IH
BH616UV8011
TYP.
1.2
--
--
--
(1)
OUTPUTS
MUST BE
STEADY
WILL BE CHANGE
FROM “H” TO “L”
WILL BE CHANGE
FROM “L” TO “H”
CHANGE :
STATE UNKNOW
CENTER LINE IS
HIGH INPEDANCE
“OFF” STATE
MAX.
7.0
--
--
--
Revision
Oct.
UNITS
uA
ns
ns
V
2008
1.2