VFC101JN BURR-BROWN [Burr-Brown Corporation], VFC101JN Datasheet - Page 9

• Manufacturer Part Number: VFC101JN
• Description: Synchronized VOLTAGE-TO-FREQUENCY CONVERTER
• Manufacturer: BURR-BROWN [Burr-Brown Corporation]

The circuit in Figure 5 operates from the minimum power
supplies, avoiding saturation of the integrator amplifier and
loss of accuracy. C
integrator voltage swing (referred to the noninverting com-
parator input). The offset voltage applied to the comparator’s
noninverting input is derived from a resistive voltage divider
from V
The relationship of the allowable operating voltage ranges
on important pins is shown in Figure 6. Note that the
integrator amplifier output cannot swing more than 0.2V
below ground. Although this is not “normal” for an opera-
tional amplifier, a special design of this type optimizes high-
frequency performance. It is this characteristic which re-
quires offsetting the noninverting comparator input in volt-
age-to-frequency mode.
FREQUENCY-TO-VOLTAGE MODE
The VFC100 can also function as a frequency-to-voltage
converter by supplying an input frequency to the comparator
input as shown in Figure 7. The input resistor, R
connected as a feedback resistor. The voltage at the integra-
tor amp output is proportional to the ratio of the input
frequency to the clock frequency. The transfer function is:
This transfer function is complementary to the voltage-to-
frequency mode transfer function, making voltage-to-fre-
quency-to-voltage conversions simple and accurate.
Direct coupling of the input frequency to the comparator is
easily accomplished by driving both comparators with
complementary frequency input signals. Alternatively, one
of the comparator inputs can be biased at half the logic
voltage (using V
driven directly.
FIGURE 6. Relationships of Allowable Voltages.
7.5V to
28.5V
> –0.2V
REF
.
> 7.5V
> –7.5V
< 0.1V
REF
V
10
OUT
and a voltage divider) and the other input
INT
7
9
6
= (f
is chosen for a +100mV to –75mV
8
OUT
/f
R
CLOCK
IN
7.5V to 28.5V
> 3V
) 20V.
5
–V
CC
+V
–V
16
CC
CC
4
IN
, is
17
18
–V
–V
9
CC
CC
+ 4V to +V
+ 4V to +V
The proper timing of the input frequency waveform is
shown in Figure 7. The input pulse should go low for one
clock cycle, centered around a falling edge of the clock. The
minimum acceptable input pulse width must fall no later
than 200ns before a negative clock edge and rise no sooner
than 200ns after the falling clock edge. An input pulse which
remains low for more than one falling edge of the clock will
produce incorrect output voltages. Positive (active high)
input pulses can be accepted by reversing the connections to
pins 14 and 15.
The integrator amplifier output is designed to drive up to
10,000pF and 5k loads in frequency-to-voltage mode. This
allows driving long lines in a large system.
Ripple voltage in the voltage output is unavoidable and is
inversely proportional to the value of the integrator capaci-
tor. Figure 8 shows the output ripple and settling time as a
function of the C
The ripple frequency is equal to the input frequency. Its
magnitude can be reduced by using a large integrator capaci-
tor value, but with the tradeoff of slow settling time in
response to an input frequency change. The settling time
constant is equal to R
output ripple and settling time can be achieved by using a
moderately low integrator capacitor value and adding a low-
pass filter on the analog output. The cutoff frequency of the
filter should be made below the lowest expected input
frequency to the frequency-to-voltage converter.
NOTE: Several useful applications circuits may be found
in the VFC100 product data sheet. These require only
minor adaptation to the different pinout and input resis-
tor configurations of the VFC101.
13
–V
Reference
Clocked
CC
Logic
CC
(5V)
CC
5V
+ 3V to +V
– 2
20
CC
INT
value.
IN
+V
One-Shot
x C
Output
CC
or C
INT
2
12
+V
. A better compromise between
OS
CC
VFC101
–V
CC
11
15
14
to 30V
–0.5V
> 2V
> 4V
15V to
36V
®