IRU3055CQ IRF [International Rectifier], IRU3055CQ Datasheet - Page 21

• Manufacturer Part Number: IRU3055CQ
• Description: POWER MANAGEMENT CHIPSET FOR 3-PHASE VRM 9.0 CONVERTERS
• Manufacturer: IRF [International Rectifier]

Calculating R22 (referring to e3R1 in Figure 22) by the
provided equation, we get
The resistor R11 and R16 (referring to c3R1 and d3R2
in Figure 22) have to be tuned. From the suggested equa-
tion, they are in a few KV range. Because resistor R11
and R16 function independent, they can be tuned sepa-
rately. First, connect the board and make the board work
first. Put no load in the output. Then replace R16 with a
5K~20K potentiometer and adjust the potentiometer so
as the output voltage is about 25mV lower than the DAC
output setting. Because the output current is zero, the
resistor R11 will not affect the output voltage. The DC
offset is only dependent on R16. Select R16 with the
tuned potentiometer value.
After R16 is tuned, replace R11 with a potentiometer.
Connect the output voltage to certain current load (for
example, half of the nominal load, 30A). Adjust the po-
tentiometer so that the output voltage has the same volt-
age drops as Intel spec requests (for example, 95mV
drop comparing with zero current condition). Then se-
lect R11 with tuned potentiometer value.
Rev. 1.4
08/13/02
Figure 23 - Test steady state output voltage for the
R22 = R173Vc/V
1.55
1.45
1.35
1.25
Comparison of Test Data with Intel Spec
1.5
1.4
1.3
circuit of IRU3055 with active droop.
0
10
Vomax(Intel spec)
Vo(typical Intel spec)
Vomin (Intel spec)
Experiment Vo (steady state)
Vset (experiment)
OFFSET
20
I
= 1K32V/25mV = 80K
O U T
30
(A)
40
50
60
www.irf.com
The test data is displayed in Figure 23. The DAC input is
01110, which refers to output voltage 1.5V. The mea-
sured DAC output V
voltage versus load current falls into the Intel specifica-
tion as shown in Figure 23.
In this figure, at light load, the output voltage almost
follows the Intel typical specification. At 40A, 50A and
60A loads, the output voltage is a slight deviation from
the typical Intel spec. The reason is because the induc-
tors get hot at high current loads. The resistance in-
creases comparing with low load condition. As a result,
there is more voltage droop than the theoretical predic-
tion, because the specification at high current has larger
tolerance. The Intel specification can be satisfied easily
with the proposed circuit.
Implement the 1.2V VID Regulator
If a Quadra-OPAMP such as LM324 is used, the addi-
tional 1.2V VID regulator as well as the power sequence
can be implemented. In application circuit Figure 20,
one OPAMP and a NPN transistor 2N3904 implement a
1.2V, 30mA VID voltage regulator. The VID voltage is
also sent to the minus input of one OPAMP. When the
VID voltage reaches 1V, the OPAMP changes to high
state and starts to charge up the RC network. The Re-
sistor R15 and the capacitor C16 function as a delay
network. 40K and 0.1mF will give about 1ms delay. In
the application circuit, C16=0.47mF, which gives about
5ms delay for a better illustration. When the voltage
across capacitor C16 reaches 1V, the OPAMP will turn
off the two NPN transistors. The soft-start capacitor of
IRU3055, C10, starts to be charged up and output volt-
age, Vo, will smoothly go into steady state.
SET
is 1.490V. The measured output
IRU3055
21