A8287 ALLEGRO [Allegro MicroSystems], A8287 Datasheet - Page 12

• Manufacturer Part Number: A8287
• Description: LNB Supply and Control Voltage Regulator
• Manufacturer: ALLEGRO [Allegro MicroSystems]

Example.
Given:
Assume:
Worst case losses can now be estimated:
and therefore
The thermal resistance required is:
V
V
I
Two-layer PCB.
Maximum ambient temperature = 70 ºC,
Maximum allowed junction temperature= 110 ºC
LOAD
Pd_control = 15 mA
IN
OUT
Pd_Rds = 0.843
(110 – 70) / 0.792 = 50.5ºC/W
= 12 V
R
Pd_sw = 70 mW
= 18 V
Pd_lin = 0.7
= 500 mA
DSBOOST
P
TOT
I
D = 1 – (12 / (18 + 0.4 + 0.7) = 0.37
V
PK
D
= 0.192 + 0.07 + 0.18 + 0.35 = 0.792 W
= 18
= 0.5 + (110 – 25)
= 0.4 V and select ∆V
×
×
2
×
0.5 = 350 mW
0.5 / (0.89
×
0.73
V
IN
100
×
= 180 mW
90
80
70
60
50
40
0.37 = 192 mW
0
×
×
A8285, 16-Pin SOIC
12) = 843 mA
2.7 mΩ= 730 mΩ
1
REG
= 0.7 V
Area (in.
Area (in
2
One side Copper
Two side Copper
2
)
2
)
R
3
ØJA
LNB Supply and Control Voltage Regulator
vs. Area Charts
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
4
Note: For the case of the A8287, the area of copper required
on each layer is approximately 1.2 in
Layout Considerations
Recommended placement of critical components and track-
ing for the A8287 is shown in the PCB Layout digagram on
the following page. It is recommended that the ground plane
be separated into two areas, referred to as switcher and con-
trol, on each layer using a ground plane. With respect to the
input connections, VIN and 0V, the two ground plane areas
are isolated as shown by the dotted line and the ground plane
areas are connected together at pins 6, 7, 18, and 19. This
confi guration minimizes the effects of the noise produced by
the switcher on the noise-sensitive sections of the circuit.
Power-related tracking from INPUT to L1, LNB (pin 17) to
L2 then OUTPUT, LX (pin 20) to D1 and L1, VBOOST (pin
23) to C4 and D1 should be as short and wide as possible.
Power components such as the boost diode D1, inductor
L1, and input/output capacitors C1, C9, and C4, should be
located as close as possible to the IC. The DiSEqC inductor
L2 should be located as far away from the boost inductor L1
to prevent potential magnetic crosstalk.
The fi lter capacitor (VREG), charge pump capacitor (VCP),
ac coupling tone detect capacitor (TDI), tone pull-down
resistor (TOUT), and LNB output capacitor/protection diode
(LNB) should be located directly next to the appropriate pin.
Where a PCB with two or more layers is used, it is recom-
mended that four thermal vias be deployed as shown in the
PCB Layout diagram. Note that adding additional vias does
not enhance the thermal characteristics.
80
70
60
50
40
0
A8287, 24-Pin SOIC
1
Area (in.
Area (in
2
One side Copper
Two side Copper
2
)
2
)
3
4
A8285/A8287
2
.
12