MB90F654A FUJITSU [Fujitsu Component Limited.], MB90F654A Datasheet - Page 53

• Manufacturer Part Number: MB90F654A
• Description: 16-bit Proprietary Microcontroller
• Manufacturer: FUJITSU [Fujitsu Component Limited.]

9. DTP/External Interrupts
(1) Register Configuration
(2) Block Diagram
The DTP (Data Transfer Peripheral) is a peripheral block that interfaces external peripherals to the F
CPU. The DTP receives DMA and interrupt processing requests from external peripherals and passes the
requests to the F
(“H” and “L”) are provided for the intelligent I/O service. For external interrupt requests, generation of interrupts
on a rising or falling edge as well as on “H” and “L” levels can be selected, giving a total of four types.
Interrupt/DTP enable register (ENIR)
Interrupt/DTP source register (EIRR)
Request level setting register (ELVR)
4
4
4
8
2
MC-16L CPU to activate the intelligent I/O service or interrupt processing. Two request levels
Gate
R/W : Readable and writable
Address : 000030
Address : 000031
Address : 000032
Address : 000033
Interrupt/DTP enable register
Interrupt/DTP source register
Request level setting register
Request F/F
H
H
H
H
bit 15
bit 15
EN7
R/W
ER7
R/W
R/W
R/W
LB3
LB7
bit 7
bit 7
bit 14
bit 14
EN6
ER6
LA3
LA7
bit 6
R/W
R/W
bit 6
R/W
R/W
bit 13
bit 13
EN5
ER5
R/W
R/W
LB2
R/W
LB6
R/W
bit 5
bit 5
Edge detect circuit
bit 12
bit 12
EN4
ER4
LA2
LA6
bit 4
bit 4
R/W
R/W
R/W
R/W
bit 11
bit 11
EN3
ER3
R/W
R/W
LB1
R/W
LB5
R/W
bit 3
bit 3
MB90650A Series
bit 10
bit 10
EN2
ER2
bit 2
bit 2
LA1
LA5
R/W
R/W
R/W
R/W
4
EN1
ER1
R/W
R/W
LB0
R/W
LB4
R/W
bit 1
bit 9
bit 1
bit 9
EN0
R/W
ER0
R/W
R/W
R/W
bit 0
bit 8
bit 0
LA0
bit 8
LA4
Request input
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
Initial value
Initial value
Initial value
Initial value
2
MC-16L
B
B
B
B
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