MB90F654A FUJITSU [Fujitsu Component Limited.], MB90F654A Datasheet - Page 64

• Manufacturer Part Number: MB90F654A
• Description: 16-bit Proprietary Microcontroller
• Manufacturer: FUJITSU [Fujitsu Component Limited.]

MB90650A Series
14. Low-power Consumption Mode (CPU Intermittent Operation Function, Oscillation
Stabilization Delay Time, Clock Multiplier Function)
The following are the operating modes: PLL clock mode, PLL sleep mode, PLL watch mode, pseudo-watch
mode, main clock mode, main sleep mode, main watch mode, main stop mode, sub clock mode, sub sleep
mode, sub watch mode, and sub stop mode. Aside from the PLL clock mode, all of the other operating modes
are low-power consumption modes.
In main clock mode and main sleep mode, the main clock (main OSC oscillation clock) and the sub clock (sub
OSC oscillation clock) operate. In these modes, the main clock divided by 2 is used as the operation clock, the
sub clock (sub OSC oscillation clock) is used as the timer clock, and the PLL clock (VCO oscillation clock) is
stopped.
In sub clock mode and sub sleep mode, only the sub clock operates. In these modes, the sub clock is used as
the operation clock, and the main clock and PLL clock are stopped.
In PLL sleep mode and main sleep mode, only the CPU’s operation clock is stopped; all clocks other than the
CPU clock operate.
In pseudo-watch mode, only the watch timer and timebase timer operate.
In PLL watch mode, main watch mode, and sub watch mode, only the watch timer operates. In this mode, only
the sub clock is used for operation, while the main clock and the PLL clock are stopped (the difference between
the PLL watch mode, the main watch mode and the sub watch mode is that it resumes operation after an interrupt
in the PLL clock mode, the main clock mode, and the sub clock mode respectively, and there is no reference
concerning about clock mode operation).
The main stop mode, sub stop mode, and hardware standby mode stop oscillation, making it possible to retain
data while consuming the least amount of power. (The difference between the main stop mode and the sub stop
mode is that it resumes operation in the main clock mode and the sub clock mode respectively, and there is no
reference concerning about stop mode operation).
The CPU intermittent operation function intermittently runs the clock supplied to the CPU when accessing
registers, on-chip memory, on-chip resources, and the external bus. Processing is possible with lower power
consumption by reducing the execution speed of the CPU while supplying a high-speed clock and using on-chip
resources.
The PLL clock multiplier can be selected as either 2, 4, 6, or 8 by setting the CS1 and CS0 bits. These clocks
are divided by 2 to be used as a machine clock.
The WS1 and WS0 bits can be used to set the main clock oscillation stabilization delay time for when stop mode
is woken up.
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