M37544 RENESAS [Renesas Technology Corp], M37544 Datasheet
M37544
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M37544 Summary of contents
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Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DESCRIPTION The 7544 Group is the 8-bit microcomputer based on the 740 fam- ily core technology. The 7544 Group has a serial I/O, 8-bit timers, a 16-bit timer, and an A/D converter, and is ...
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... RESET CNV X Fig. 3 Pin configuration (42S1M type) Rev.1.04 2004.06.08 page REJ03B0012-0104Z ) M37544M2-XXXGP 28 CLK 29 RDY M37544G2GP Package type : 32P6U ...
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... RDY P1 /CNTR / / Fig. 4 Pin configuration (36PJW-A type) Rev.1.04 2004.06.08 page REJ03B0012-0104Z M37544M2-XXXHP 31 32 M37544G2HP (Note Package type: 36PJW-A [N.C (LED ) (LED ) 16 2 ...
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Group FUNCTIONAL BLOCK Fig. 5 Functional block diagram (32P4B package) Rev.1.04 2004.06.08 page REJ03B0012-0104Z ...
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Group Fig. 6 Functional block diagram (32P6U package) Rev.1.04 2004.06.08 page REJ03B0012-0104Z ...
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Group Fig. 7 Functional block diagram (36PJW package) Rev.1.04 2004.06.08 page REJ03B0012-0104Z ...
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Group PIN DESCRIPTION Table 1 Pin description Pin Name Vcc, Vss Power source •Apply voltage of 4 Vcc, and Vss. V Analog reference •Reference voltage input pin for A/D converter REF voltage ...
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... Part number ROM size for User () M37544M2-XXXSP 8192 M37544M2-XXXGP (8062) M37544M2-XXXHP M37544G2SP M37544G2GP M37544G2HP (Note) M37544RSS Note: Only ES version (MP: no plan) Rev.1.04 2004.06.08 page REJ03B0012-0104Z Memory size ROM/PROM size .............................................................. 8 K bytes RAM size ......................................................................... 256 bytes Package 32P4B .................................................. 32-pin plastic molded SDIP 32P6U-A ...
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Group FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) The MCU uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine-language instructions or the SERIES 740 <SOFTWARE> USER’S MANUAL for details on each ...
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Group Interrupt request M (S) (S) Store Return Address on Stack M (S) (S) Subroutine Execute RTS (S) Restore Return Address ( (S) ( (S) H Note : The condition to enable the interrupt Fig. ...
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Group Processor status register (PS) The processor status register is an 8-bit register consisting of flags which indicate the status of the processor after an arithmetic operation. Branch operations can be performed by testing the Carry (C) flag, Zero ...
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... disable to write any data to the bit. However, by reset the bit is initialized and can be rewritten, again. (It is not disable to write any data to the bit for emulator MCU “M37544RSS”.) oscillation is selected. /quartz-crystal Do not use these when an RC oscillation is selected. ) ...
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Group Memory Special function register (SFR) area The SFR area in the zero page contains control registers such as I/O ports and timers. RAM RAM is used for data storage and for a stack area of subroutine calls and ...
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Group Port P0 (P0) 0000 16 0001 Port P0 direction register (P0D) 16 Port P1 (P1) 0002 16 Port P1 direction register (P1D) 0003 16 0004 Port P2 (P2) 16 Port P2 direction register (P2D) 0005 16 Port P3 ...
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Group I/O Ports [Direction registers] PiD The I/O ports have direction registers which determine the input/ output direction of each pin. Each bit in a direction register corre- sponds to one pin, and each pin can be set to ...
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Group Table 5 I/O port function table Pin Name Input/output P0 /CNTR I/O port P0 I/O individual bits /TX 3 OUT P0 – /RxD I/O port ...
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Group (1)Port P0 0 Pull-up control Direction register Port latch Data bus CNTR interrupt input 1 To key input interrupt generating circuit (3)Port P0 3 Pull-up control Direction register Data bus Port latch Timer output P0 /TX 3 output ...
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Group (7) Port P1 3 Serial I/O mode selection bit Serial I/O enable bit S output enable bit RDY Direction register Data bus Port latch Serial I/O ready output (9) Ports P2 – Direction register Data bus ...
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Group Interrupts Interrupts occur by 12 different sources : 5 external sources, 6 in- ternal sources and 1 software source. Interrupt control All interrupts except the BRK instruction interrupt have an interrupt request bit and an interrupt enable bit, ...
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Group Interrupt request bit Interrupt enable bit Interrupt disable flag I Fig. 19 Interrupt control Fig. 20 Structure of Interrupt-related registers Rev.1.04 2004.06.08 page REJ03B0012-0104Z BRK instruction Reset b0 Interrupt edge ...
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Group Key Input Interrupt (Key-On Wake-Up) A key-on wake-up interrupt request is generated by applying “L” level to any pin of port P0 that has been set to input mode. In other words generated when the AND ...
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Group Timers The 7544 Group has 3 timers: timer 1, timer A and timer X. The division ratio of every timer and prescaler is 1/(n+1) provided that the value of the timer latch or prescaler is n. All the ...
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Group (3) Event counter mode Timer A counts signals input from the P0 Except for this, the operation in event counter mode is the same as in timer mode. The active edge of CNTR pin input signal can be ...
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Group Timer X Timer 8-bit timer and counts the prescaler X output. When Timer X underflows, the timer X interrupt request bit is set to “1”. Prescaler 8-bit prescaler and counts the signal ...
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Group b7 b0 Timer X mode register (TXM : address 002B Timer X operating mode bits Timer mode Pulse output mode Event counter mode Pulse ...
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Group On-chip oscillator clock RING CNTR edge switch bit P0 /CNTR 0 1 f(X )/16 IN f(X )/2 IN On-chip oscillator clock RING Timer A operation mode bit Fig. 26 Block diagram of timer 1 and timer A f(X ...
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Group Serial I/O Serial I/O Serial I/O can be used as either clock synchronous or asynchro- nous (UART) serial I/O. A dedicated timer is also provided for baud rate generation CLK ...
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Group (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O mode selection bit of the serial I/O control register to “0”. Eight serial data transfer formats can be ...
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Group [Transmit buffer register/receive buffer register (TB/RB)] 0018 16 The transmit buffer register and the receive buffer register are lo- cated at the same address. The transmit buffer is write-only and the receive buffer is read-only character ...
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Group b0 b7 Serial I/O status register (SIOSTS : address 0019 Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: ...
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Group A/D Converter The functional blocks of the A/D converter are described below. [A/D conversion register] AD The A/D conversion register is a read-only register that stores the result of A/D conversion. Do not read out this register during ...
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Group Watchdog Timer The watchdog timer gives a means for returning to a reset status when the program fails to run on its normal loop due to a runaway. The watchdog timer consists of an 8-bit watchdog timer H ...
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Group Reset Circuit The microcomputer is put into a reset status by holding the RE- SET pin at the “L” level for more when the power source voltage is 4.5 to 5.5 V and X is ...
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Group (1) Port P0 direction register (2) Port P1 direction register (3) Port P2 direction register (4) Port P3 direction register (5) Pull-up control register (6) Port P1P3 control register (7) Serial I/O status register (8) Serial I/O control ...
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... Connect the external circuit of resistor R M37544 and the capacitor C at the shortest distance. The frequency is af- X OUT fected by a capacitor, a resistor and a micro- R computer. So, set the constants C within the range of the frequency limits. M37544 OUT Open External oscillation circuit ...
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... After rewriting it is disable to write any data to the bit. (The emulator MCU “M37544RSS” is excluded.) Also, when the read-modify-write instructions (SEB, CLB) are ex- ecuted to bits and 7, bits 5, 1 and 0 are locked. ...
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... Oscillation stop detection status bit is initialized by the following operation. (1) External reset (2) Write “0” data to the ceramic or RC oscillation stop detection function active bit. • The oscillation stop detection circuit is not included in the emu- lator MCU “M37544RSS”. Rev.1.04 2004.06.08 page REJ03B0012-0104Z b7 ...
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Group On-chip oscillator mode RING On-chip oscillator STP instruction Reset Interrupt disable flag l Interrupt request Fig. 46 Block diagram of internal clock generating circuit (for ceramic/quartz-crystal resonator OUT IN Delay ...
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Group Interrupt Interrupt STP instruction State 1 Operation clock source: CPUM 0 Operation clock source f(X ) (Note 1) IN f(X ) (Note 1) IN f(X ) oscillation enabled IN f(X ) oscillation enabled IN On-chip oscillator ...
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Group NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after reset are undefined except for the interrupt disable flag I which is “1”. After reset, initialize flags which affect program execution. In particular, ...
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Group NOTES ON USE Countermeasures against noise 1. Shortest wiring length (1) Package Select the smallest possible package to make the total wiring length short. <Reason> The wiring length depends on a microcomputer package. Use of a small package, ...
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Group (5) Wiring to V pin of One Time PROM version PP Connect an approximately 5 k resistor to the V possible in series and also to the Vss pin. When not connecting the resistor, make the length of ...
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Group 4. Oscillator concerns So that the product obtains the stabilized operation clock on the user system and its condition, contact the resonator manufacturer and select the resonator and oscillation circuit constants. Be careful especially when range of voltage ...
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Group 5. Setup for I/O ports Setup I/O ports using hardware and software as follows: <Hardware> • Connect a resistor of 100 or more to an I/O port in series. <Software> • As for an input port, read data ...
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... Group PROM Mode M37544G2SP/GP (referred to as “the MCU”) has a PROM Mode as well as the normal operation mode. PROM Mode enables an external device (referred to as “Programmer”) to read and pro- gram the built-in EPROM via a minimum number of serial I/O pins by sending commands to control the MCU. ...
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... ESCLK /CNTR Fig. 61 “Mad Dog Entry” Pin Diagram (32P6U-A) Rev.1.04 2004.06.08 page REJ03B0012-0104Z ) CLK M37544G2GP 29 RDY (LED )/INT (LED ) (LED ) ...
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Group Precaution for Handling One-Time-Programmable Devices Our company ships one-time-programmable version MCUs (One- Time PROM MCU) without being screened by the PROM writing test. To ensure the reliability of the MCU, We recommend that the user performs the program ...
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Group ROM Code Access Protection We would like to support a simple ROM code protection function that prevents a party other than the ROM-code owner to read and reprogram the builit-in PROM code of the MCU. The MCU has ...
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... Group ELECTRICAL CHARACTERISTICS 1.7544Group Applied to: M37544M2-XXXSP/GP/HP, M37544G2SP/GP/HP(Note) Note: M37544G2HP: Only ES version (MP: no plan) Absolute Maximum Ratings Table 9 Absolute maximum ratings Symbol Parameter V Power source voltage CC V Input voltage I P0 – – ______ V Input voltage RESET ...
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Group Recommended Operating Conditions Table 10 Recommended operating conditions (1) (V Symbol V Power source voltage (ceramic) CC Power source voltage (RC) V Power source voltage SS V Analog reference voltage REF V “H” input voltage IH P0 –P0 ...
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Group Recommended Operating Conditions (continued) Table 11 Recommended operating conditions (2) (V Symbol I “H” peak output current (Note 1) OH(peak) P0 – – – “L” peak output current ...
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Group Electrical Characteristics Table 12 Electrical characteristics (1) (V Symbol Parameter V “H” output voltage OH P0 – – – “L” output voltage OL P1 – –P2 ...
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Group Electrical Characteristics (continued) Table 13 Electrical characteristics (2) (V Symbol Parameter I High-speed mode, f(X Power source CC current Output transistors “off” Double-speed mode, f(X Output transistors “off” Middle-speed mode, f(X Output transistors “off” On-chip oscillator operation mode, ...
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Group A/D Converter Characteristics Table 14 A/D Converter characteristics (V Symbol Parameter — Resolution ABS Absolute accuracy (quantification error excluded) t Conversion time CONV R Ladder resistor LADDER I Reference power source VREF input current I A/D port input ...
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Group Switching Characteristics Table 16 Switching characteristics (V Symbol Serial I/O clock output “H” pulse width WH CLK Serial I/O clock output “L” pulse width WL CLK t (S –TxD) Serial I/O output ...
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Group CNTR 0 CNTR 1 INT , INT 0 1 RESET CLK R D (at receive (at transmit) X Fig. 65 Timing chart Rev.1.04 2004.06.08 page REJ03B0012-0104Z t (CNTR ) ...
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Group PACKAGE OUTLINE 32P4B Recommended EIAJ Package Code JEDEC Code SDIP32-P-400-1.78 – SEATING PLANE 32P6U-A Recommended EIAJ Package Code JEDEC Code LQFP32-P-0707-0.80 – Rev.1.04 2004.06.08 page ...
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Group 36PJW-A EIAJ Package Code JEDEC Code WQFN36-P-0606-0.50 – Rev.1.04 2004.06.08 page REJ03B0012-0104Z Weight(g) Lead Material 0.83 Cu Alloy 4.26 (Typ ...
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Group APPENDIX NOTES ON PROGRAMMING 1. Processor Status Register (1) Initializing of processor status register Flags which affect program execution must be initialized after a re- set. In particular essential to initialize the T and D flags ...
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Group 6. Read-modify-write instruction Do not execute a read-modify-write instruction to the read invalid address (SFR). The read-modify-write instruction operates in the following se- quence: read one-byte of data from memory, modify the data, write the data back to ...
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Group Termination of Unused Pins 1. Terminate unused pins Perform the following wiring at the shortest possible distance ( less) from microcomputer pins. (1) I/O ports Set the I/O ports for the input mode and connect each ...
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Group Notes on Timers 1. When 255) is written to a timer latch, the frequency divi- sion ratio is 1/(n+1). 2. When a count source of timer X is switched, stop a count of the timer. ...
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Group Notes on Serial I/O 1. Clock synchronous serial I/O (1) When the transmit operation is stopped, clear the serial I/O en- able bit (bit 7) and the transmit enable bit (bit 4 of serial I/O control register (address ...
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Group 4. I/O pin function when serial I/O is enabled. The pin functions and P1 2 CLK 3 follows according to the setting values of a serial I/O mode selec- tion bit (bit 6 of serial ...
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Group Notes on Clock Generating Circuit 1. Switch of ceramic/quartz-crystal oscillation and RC oscillation After releasing reset, the oscillation mode selection bit (bit 5 of CPU mode register (address “0” (ceramic/quartz-crystal 16 oscillation selected). When the ...
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Group Electric Characteristic Differences Among Mask ROM and One Time PROM Version MCUs There are differences in electric characteristics, operation margin, noise immunity, and noise radiation among mask ROM and One Time PROM version MCUs due to the differences ...
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... Oscillation stop detection circuit revised. Fig. 46, Fig bit name revised. Countermeasure against noise added. (NOTES ON PERIPHERAL FUNCTIONS described previously here are included in APPENDIX at the end of this data sheet.) Part number: M37544M2-XXXHP, M37544G2HP added. PACKAGE OUTLINE: 36PJW-A added. APPENDIX added. Words standardized: On-chip oscillator, A/D converter (1/1) ...
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Sales Strategic Planning Div. Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble ...