MCF52274 FREESCALE [Freescale Semiconductor, Inc], MCF52274 Datasheet - Page 26

• Manufacturer Part Number: MCF52274
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

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Electrical Characteristics
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DD10 Input Data Hold Relative to DQS
DD11 DQS falling edge from SDCLK rising (output hold time) t
Num
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
The frequency of operation is either 2x or 4x the FB_CLK frequency of operation. FlexBus and SDRAM clock operate at the
same frequency as the internal bus clock.
SD_CLK is one SDRAM clock in ns.
Pulse-width high plus pulse-width low cannot exceed minimum or maximum clock period.
Command output valid should be one-half the memory bus clock (SD_CLK) plus some minor adjustments for process,
temperature, and voltage variations.
This specification relates to the required input setup time of today’s DDR memories. The device’s output setup should be larger
than the input setup of the DDR memories. If it is not larger, then the input setup on the memory will be in violation.
MEM_DATA[31:24] is relative to MEM_DQS[3], MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to
MEM_DQS[1], and MEM_DATA[7:0] is relative MEM_DQS[0].
The first data beat will be valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats
will be valid for each subsequent DQS edge.
This specification relates to the required hold time of today’s DDR memories. MEM_DATA[31:24] is relative to MEM_DQS[3],
MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to MEM_DQS[1], and MEM_DATA[7:0] is relative
MEM_DQS[0].
Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line
becomes valid. This input skew must include DDR memory output skew and system-level board skew (due to routing or other
factors).
Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line becomes
invalid.
Frequency of Operation
Clock Period
Pulse Width High
Pulse Width Low
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] - Output Valid
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] - Output Hold
Write Command to first DQS Latching Transition
Data and Data Mask Output Setup (DQ→DQS)
Relative to DQS (DDR Write Mode)
Data and Data Mask Output Hold (DQS→DQ) Relative
to DQS (DDR Write Mode)
Input Data Skew Relative to DQS (Input Setup)
Characteristic
MCF5227x ColdFire
Preliminary—Subject to Change Without Notice
Table 15. DDR Timing Specifications
®
Microprocessor Data Sheet, Rev. 6
t
t
t
Symbol
SDCHACV
DQLSDCH
SDCHACI
CMDVDQ
t
t
t
t
DQDMV
t
DDCKH
t
DDCKL
t
DQDMI
t
DDCK
DDSK
DVDQ
DIDQ
0.25 × SD_CLK
+ 0.5ns
TBD
12.0
0.45
0.45
Min
2.0
1.5
1.0
0.5
—
—
—
0.5 × SD_CLK
83.33
+ 1.0
Max
TBD
0.55
0.55
1.25
—
—
—
—
—
1
Freescale Semiconductor
SD_CLK
SD_CLK
SD_CLK
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Notes
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