LM3S101-IRN20 ETC2 [List of Unclassifed Manufacturers], LM3S101-IRN20 Datasheet - Page 144
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LM3S101-IRN20
Manufacturer Part Number
LM3S101-IRN20
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S101-IRN20.pdf
(300 pages)
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Part Number
Manufacturer
Quantity
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Part Number:
LM3S101-IRN20C0X
Manufacturer:
LUMINARYM
Quantity:
20 000
- Current page: 144 of 300
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General-Purpose Timers
9.3.5
9.3.6
144
4.
5.
6.
7.
8.
9.
In Input Edge Count Mode, the timer stops after the desired number of edge events has been
detected. To re-enable the timer, ensure that the TnEN bit is cleared and repeat steps 4-9.
16-Bit Input Edge Timing Mode
A timer is configured to Input Edge Timing mode by the following sequence:
1.
2.
3.
4.
5.
6.
7.
8.
In Input Edge Timing mode, the timer continues running after an edge event has been detected,
but the timer interval can be changed at any time by writing the GPTMTnILR register. The change
takes effect at the next cycle after the write.
16-Bit PWM Mode
A timer is configured to PWM mode using the following sequence:
1.
2.
3.
4.
5.
6.
Configure the type of event(s) that the timer captures by writing the TnEVENT field of the
GPTM Control (GPTMCTL) register.
Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.
Load the desired event count into the GPTM Timern Match (GPTMTnMATCHR) register.
If interrupts are required, set the CnMIM bit in the GPTM Interrupt Mask (GPTMIMR) register.
Set the TnEN bit in the GPTMCTL register to enable the timer and begin waiting for edge
events.
Poll the CnMRIS bit in the GPTMRIS register or wait for the interrupt to be generated (if
enabled). In both cases, the status flags are cleared by writing a 1 to the CnMCINT bit of the
GPTM Interrupt Clear (GPTMICR) register.
Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
Write the GPTM Configuration (GPTMCFG) register with a value of 0x4.
In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x1 and the TnMR
field to 0x3.
Configure the type of event that the timer captures by writing the TnEVENT field of the GPTM
Control (GPTMCTL) register.
Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.
If interrupts are required, set the CnEIM bit in the GPTM Interrupt Mask (GPTMIMR) register.
Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and start
counting.
Poll the CnERIS bit in the GPTMRIS register or wait for the interrupt to be generated (if
enabled). In both cases, the status flags are cleared by writing a 1 to the CnECINT bit of the
GPTM Interrupt Clear (GPTMICR) register. The time at which the event happened can be
obtained by reading the GPTM Timern (GPTMTnR) register.
Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
Write the GPTM Configuration (GPTMCFG) register with a value of 0x4.
In the GPTM Timer Mode (GPTMTnMR) register, set the TnAMS bit to 0x1, the TNCMR bit to
0x0, and the TnMR field to 0x2.
Configure the output state of the PWM signal (whether or not it is inverted) in the TnEVENT
field of the GPTM Control (GPTMCTL) register.
Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.
Load the GPTM Timern Match (GPTMTnMATCHR) register with the desired value.
Preliminary
October 5, 2006
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