M38867E8AHP MITSUBISHI [Mitsubishi Electric Semiconductor], M38867E8AHP Datasheet - Page 49

• Manufacturer Part Number: M38867E8AHP
• Description: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER??
• Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]

Example of Master Transmission
An example of master transmission in the standard clock mode, at
the S
shown below.
Example of Slave Reception
An example of slave reception in the high-speed clock mode, at
the S
using the addressing format is shown below.
register (address 0013
Set the ACK return mode and S
the I
transmission/reception mode can become initializing condition.
control register (address 0015
register (address 0014
high-order 7 bits of the I
and set “0” in the least significant bit.
ate a START condition. At this time, an S
ACK clock automatically occur.
Set transmit data in the I
At this time, an S
ate a STOP condition if ACK is not returned from slave
reception side or transmission ends.
Set the no ACK clock mode and S
When a START condition is received, an address comparison is
• When the transmitted addresses agree with the address set
• In the cases other than the above AD0 and AAS of the I
When receiving control data of more than 1 byte, repeat step
Set a slave address in the high-order 7 bits of the I
Set “00
Set a communication enable status by setting “08
Confirm the bus free condition by the BB flag of the I
Set the address data of the destination of transmission in the
Set “F0
When transmitting control data of more than 1 byte, repeat step
Set “D0
Set a slave address in the high-order 7 bits of the I
Set “00
Set a communication enable status by setting “08
•When all transmitted addresses are “0” (general call):
Set dummy data in the I
When a STOP condition is detected, the communication ends.
register (address 0013
in the I
transmission/reception mode can become initializing condition.
control register (address 0015
performed.
AD0 of the I
and an interrupt request signal occurs.
in
ASS of the I
and an interrupt request signal occurs.
tus register (address 0014
request signal occurs.
.
CL
CL
2
:
C clock control register (address 0016
frequency of 400 kHz, in the ACK non-return mode and
frequency of 100 kHz and in the ACK return mode is
2
16
16
16
16
C clock control register (address 0016
” in the I
” in the I
” in the I
” in the I
2
2
C status register (address 0014
C status register (address 0014
CL
2
2
2
2
C status register (address 0014
C status register (address 0014
C status register (address 0014
C status register (address 0014
and an ACK clock automatically occur.
16
16
16
2
2
2
) and “0” into the RBW bit.
).
C data shift register (address 0012
) and “0” in the RBW bit.
C data shift register (address 0012
C data shift register (address 0012
16
16
16
) are set to “0” and no interrupt
CL
).
).
CL
= 100 kHz by setting “85
= 400 kHz by setting “25
CL
16
).
for 1 byte and an
16
16
16
) is set to “1”
).
) is set to “1”
16
16
16
16
2
2
” in the I
” in the I
16
) to gener-
16
C address
) to gener-
C address
2
) so that
) so that
C status
2
C sta-
16
16
16
” in
16
2
16
2
).
C
C
).
)
”
.
(1) Read-modify-write instruction
The precautions when the read-modify-write instruction such as
SEB, CLB etc. is executed for each register of the multi-master
I
• I
• I
• I
• I
• I
• I
2
C-BUS interface are described below.
When executing the read-modify-write instruction for this regis-
ter during transfer, data may become a value not intended.
When the read-modify-write instruction is executed for this regis-
ter at detecting the STOP condition, data may become a value
not intended. It is because H/W changes the read/write bit
(RBW) at the above timing.
Do not execute the read-modify-write instruction for this register
because all bits of this register are changed by H/W.
When the read-modify-write instruction is executed for this regis-
ter at detecting the START condition or at completing the byte
transfer, data may become a value not intended. Because H/W
changes the bit counter (BC0-BC2) at the above timing.
The read-modify-write instruction can be executed for this regis-
ter.
0017
The read-modify-write instruction can be executed for this regis-
ter.
Precautions when using multi-master I
BUS interface
2
2
2
2
2
2
C data shift register (S0: address 0012
C address register (S0D: address 0013
C status register (S1: address 0014
C control register (S1D: address 0015
C clock control register (S2: address 0016
C START/STOP condition control register (S2D: address
16
)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
16
)
3886 Group
16
16
16
)
)
)
16
)
2
C-
49