EP7312-CB-90 CIRRUS [Cirrus Logic], EP7312-CB-90 Datasheet
EP7312-CB-90
Related parts for EP7312-CB-90
EP7312-CB-90 Summary of contents
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... tro lle r S RAM I/F S DRAM I/F MEMORY and STORAGE C opyright Cirrus Logic, Inc. 2003 © (All Rights Reserved) EP7312 Data Sheet High-Performance, Audio Interface ™ EP7312 is designed for ultra-low- operating systems like ® ® CE and Linux . & ers In terru & ...
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... I Package — 208-Pin LQFP — 256-Ball PBGA — 204-Ball TFBGA I The fully static EP7312 is optimized for low power dissipation and is fabricated on a 0.25 micron CMOS process The EP7312 integrates an interface to enable a direct connection to many low cost, low power, high quality audio converters. In particular, high quality ADCs, ...
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... Table of Contents FEATURES ...........................................................................................................................................1 OVERVIEW ...........................................................................................................................................1 FEATURES (cont) .......................................................................................................................................................2 OVERVIEW (cont.) ......................................................................................................................................................2 Description of the EP7312’s Components, Functionality, and Interfaces ....................................6 Processor Core - ARM720T ..................................................................................................................................6 Power Management ..............................................................................................................................................6 MaverickKey™ Unique ID ......................................................................................................................................6 Memory Interfaces .................................................................................................................................................6 Digital Audio Capability .........................................................................................................................................7 Universal Asynchronous Receiver/Transmitters (UARTs) .....................................................................................7 Digital Audio Interface (DAI) ..................................................................................................................................7 CODEC Interface ..................................................................................................................................................8 SSI2 Interface ........................................................................................................................................................8 Synchronous Serial Interface ...
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... JTAG Interface .................................................................................................................................................... 29 Packages ............................................................................................................................................ 30 208-Pin LQFP Package Characteristics ............................................................................................................. 30 EP7312 208-Pin LQFP ............................................................................................................................ 30 208-Pin LQFP Pin Diagram ................................................................................................................................ 31 EP7312 ............................................................................................................................................... 31 208-Pin LQFP Numeric Pin Listing ..................................................................................................................... 32 204-Ball TFBGA Package Characteristics .......................................................................................................... 38 204-Ball TFBGA Pinout (Top View) ..................................................................................................................... 39 204-Ball TFBGA Ball Listing ............................................................................................................................... 40 256-Ball PBGA Package Characteristics ............................................................................................................ 46 256-Ball PBGA Pinout (Top View) ....................................................................................................................... 48 256-Ball PBGA Ball Listing ...
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... List of Figures Figure 1. A Fully-Configured EP7312-Based System ................................................................................................... 12 Figure 2. Legend for Timing Diagrams ......................................................................................................................... 15 Figure 3. SDRAM Load Mode Register Cycle Timing Measurement ............................................................................ 17 Figure 4. SDRAM Burst Read Cycle Timing Measurement .......................................................................................... 18 Figure 5. SDRAM Burst Write Cycle Timing Measurement .......................................................................................... 19 Figure 6. SDRAM Refresh Cycle Timing Measurement ................................................................................................ 20 Figure 7. Static Memory Single Read Cycle Timing Measurement ...............................................................................22 Figure 8 ...
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... EP7312 through the use of laser probing technology. These IDs can then be used to match secure copyrighted content with the ID of the target device the EP7312 is powering, and then deliver the copyrighted information over a secure connection. In addition, secure transactions can benefit by also matching device IDs to server IDs. MaverickKey IDs provide a level of hardware security required for today’ ...
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... TXD[2] RXD[2] LEDDRV PHDIN Digital Audio Interface (DAI) The EP7312 integrates an interface to enable a direct connection to many low cost, low power, high quality audio converters. In particular, the DAI can directly interface with the Crystal audio DACs and the Crystal Some of these devices feature digital bass and treble boost, digital volume control and compressor-limiter functions ...
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... Note: See Table 18 on page 11 for information on pin multiplexes. 8 Synchronous Serial Interface The EP7312 Synchronous Serial Interface has these features: • ADC (SSI) Interface: Master mode only; SPI and Microwire1-compatible (128 kbps operation) • Selectable serial clock polarity Table 8 assignments. Pin Description ...
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... EINT[3] nEXTFIQ nMEDCHG/nBROM Note: Real-Time Clock The EP7312 contains a 32-bit Real Time Clock (RTC) that can be written to and read from in the same manner as the timer counters. It also contains a 32-bit output match register which can be programmed to generate an interrupt. • Driven by an external 32.768 kHz crystal oscillator Table 12 shows the Real-Time Clock pin assignments ...
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... The internal 128-byte Boot ROM facilitates download of GPIO port D saved code to the on-board SRAM/FLASH. GPIO port E Packaging GPIO port E The EP7312 is available in a 208-pin LQFP package, 256- for ball PBGA package 204-ball TFBGA package. ® C opyright Cirrus Logic, Inc. 2003 © ...
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... CODEC. The selection between SSI2 and the CODEC is controlled by the state of the SERSEL bit in SYSCON2. The choice between the SSI2, CODEC, and the DAI is controlled by the DAISEL bit in SYSCON3 (see the EP7312 User’s Manual for more information). Table 18. DAI/SSI2/CODEC Pin Multiplexing Pin I/O ...
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... FLASH FLASH EXTERNAL MEMORY- BUFFERS MAPPED EXPANSION BUFFERS ADDITIONAL I/O AND LATCHES Note: A system can only use one of the following peripheral interfaces at any given time: SSI2,CODEC or DAI. 12 EP7312 completes a low-power system solution. All necessary interface logic is integrated on-chip. MOSCIN DD[0-3] RTCIN COL[0-7] D[0-31] PA[0-7] PB[0-7] A[0-27] nMOE PD[0-7] ...
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... High-Performance, Low-Power System on Chip = 0 V over an operating temperature of 0°C SS Unit Conditions + 0 2 DDIO DDIO DDIO VIL to VIH - V IOH = 0 IOH = IOH = IOL = –0 IOL = – IOL = –12 mA VIN = V or GND µA DD VOUT = V or GND µ EP7312 13 ...
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... EP7312 High-Performance, Low-Power System on Chip Symbol Parameter COUT Output capacitance CI/O Transceiver capacitance Standby current consumption IDD STANDBY Core, Osc, RTC @2 I/O @ 3.3 V Standby current consumption IDD STANDBY Core, Osc, RTC @2 I/O @ 3.3 V Standby current consumption IDD STANDBY Core, Osc, RTC @2 I ...
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... Figure 2. Legend for Timing Diagrams = 0 V over an operating temperature of -40°C to +85°C. Pin loadings opyright Cirrus Logic, Inc. 2003 © (All Rights Reserved) High-Performance, Low-Power System on Chip EP7312 15 ...
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... EP7312 High-Performance, Low-Power System on Chip SDRAM Interface Figure 3 through Figure 6 define the timings associated with all phases of the SDRAM. The following table contains the values for the timings of each of the SDRAM modes. Parameter SDCLK rising edge to SDCS assert delay time SDCLK rising edge to SDCS deassert delay time ...
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... The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading. Designers should take care to ensure that delays between SDRAM control and data signals are approximately equal DS508PP5 High-Performance, Low-Power System on Chip t CSd t RAd t CAd t ADx t MWd C opyright Cirrus Logic, Inc. 2003 © (All Rights Reserved) EP7312 17 ...
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... EP7312 High-Performance, Low-Power System on Chip SDRAM Burst Read Cycle SDCLK t CSa t SDCS CSd t RAa t SDRAS RAd SDCAS t ADv ADDR DATA SDQM [0:3] SDMWE Note: 1. Timings are shown with CAS latency = 2 2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading. ...
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... CSd CSd t RAd t CAa t CAd t t ADv ADv ADRAS t DAd MWa Figure 5. SDRAM Burst Write Cycle Timing Measurement C opyright Cirrus Logic, Inc. 2003 © (All Rights Reserved) High-Performance, Low-Power System on Chip ADCAS DAd DAd DAd MWd EP7312 D4 19 ...
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... EP7312 High-Performance, Low-Power System on Chip SDRAM Refresh Cycle SDCLK SDCS SDRAS SDCAS SDATA ADDR SDQM [3:0] SDMWE Note: 1. Timings are shown with CAS latency = 2 2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading. ...
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... Ah t MWd t MWh t MOEd t MOEh t HWd t WDd Dnv WRd t EXs t EXh C opyright Cirrus Logic, Inc. 2003 © (All Rights Reserved) EP7312 Min Typ Max Unit ...
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... EP7312 High-Performance, Low-Power System on Chip Static Memory Single Read Cycle EXPCLK t CSd nCS nMWE nMOE t HWd HALF- WORD t WDd WORD D EXPRDY t WRd WRITE Figure 7. Static Memory Single Read Cycle Timing Measurement Note: 1. The cycle time can be extended by integer multiples of the clock period ( MHz MHz ...
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... Address, Data, Halfword, Word, and Write hold state until next cycle. DS508PP5 t CSd MWd MWh EXs EXh C opyright Cirrus Logic, Inc. 2003 © (All Rights Reserved) High-Performance, Low-Power System on Chip t CSh EP7312 23 ...
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... EP7312 High-Performance, Low-Power System on Chip Static Memory Burst Read Cycle EXPCLK t CSd nCS nMWE t MOEd nMOE t HWd HALF WORD t WORD WDd D EXPRDY t WRd WRITE Note: 1. Four cycles are shown in the above diagram (minimum wait states, 1-0-0-0). This is the maximum number of consecutive cycles that can be driven ...
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... Ah t MWd t t MWh MWh Dnv Dv Dnv t EXh Figure 10. Static Memory Burst Write Cycle Timing Measurement C opyright Cirrus Logic, Inc. 2003 © (All Rights Reserved) High-Performance, Low-Power System on Chip MWd MWd t MWh Dnv Dv EP7312 t CSh t MWh 25 ...
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... EP7312 High-Performance, Low-Power System on Chip SSI1 Interface Parameter ADCCLK falling edge to nADCCSS deassert delay time ADCIN data setup to ADCCLK rising edge time ADCIN data hold from ADCCLK rising edge time ADCCLK falling edge to data valid delay time ADCCLK falling edge to data invalid delay time ...
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... Max t 185 2050 clk_per t 925 1025 clk_high t 925 1025 clk_low clkrf FRd FRa t 960 990 FR_per RXs RXh TXd t 960 990 TXv t clk_high clk_low EP7312 Unit ...
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... EP7312 High-Performance, Low-Power System on Chip LCD Interface Parameter CL[2] falling to CL[1] rising delay time CL[1] falling to CL[2] rising delay time CL[1] falling to FRM transition time CL[1] falling to M transition time CL[2] rising to DD (display data) transition time CL[2] t CL1d CL[1] FRM M t DDd DD [3: CL2d t FRMd t Md Figure 13. LCD Controller Timing Measurement C opyright Cirrus Logic, Inc. 2003 © ...
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... High-Performance, Low-Power System on Chip Symbol t clk_per t clk_high t clk_low t JPs t JPh t JPco t JPzx t JPxz t JPh t JPs t JPco Figure 14. JTAG Timing Measurement C opyright Cirrus Logic, Inc. 2003 © (All Rights Reserved) EP7312 Min Max Units ...
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... LQFP Pin 1 Indicator 1.35 (0.053) 0.45 (0.018) 1.45 (0.057) 0.75 (0.030) Figure 15. 208-Pin LQFP Package Outline Drawing Figure 16. For pin descriptions see the EP7312 User’s Manual. C opyright Cirrus Logic, Inc. 2003 © (All Rights Reserved) 27.80 (1.094) 28.20 (1.110) 1.00 (0.039) BSC 0° MIN 7° MAX ...
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... Figure 16. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram Note: 1. N/C should not be grounded but left as no connects. DS508PP5 High-Performance, Low-Power System on Chip EP7312 208-Pin LQFP (Top View) C opyright Cirrus Logic, Inc. 2003 © (All Rights Reserved) EP7312 D[25] 104 A[25]/DRA[2] 103 D[26] 102 A[26]/DRA[1] 101 D[27] 100 ...
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... EP7312 High-Performance, Low-Power System on Chip 208-Pin LQFP Numeric Pin Listing Pin Signal No. 1 nCS[5] 2 VDDIO 3 VSSIO 4 EXPCLK 5 WORD 6 WRITE/nSDRAS 7 RUN/CLKEN 8 EXPRDY 9 TXD[2] 10 RXD[2] 11 TDI 12 VSSIO 13 PB[7] 14 PB[6] 15 PB[5] 16 PB[4] 17 PB[3] 18 PB[2] 19 PB[1] 20 PB[0] 21 VDDIO 22 TDO 23 PA[7] 24 PA[6] 25 PA[5] 26 PA[4] 27 PA[3] 28 PA[2] 29 PA[1] 30 PA[0] 31 LEDDRV 32 TXD[1] 33 VSSIO 34 PHDIN 35 CTS 36 RXD[1] ...
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... I/O DAI/CODEC/SSI2 frame sync I SSI1 ADC serial input O SSI1 ADC chip select Core ground Core Pwr Core power, 2.5 V Pad Gnd I/O ground Pad Pwr Digital I/O power, 3.3 V I/O PWM drive output I/O PWM drive output O SSI1 ADC serial clock O SSI1 ADC serial data output EP7312 33 ...
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... EP7312 High-Performance, Low-Power System on Chip Pin Signal No. 79 SMPCLK 80 FB[1] 81 VSSIO 82 FB[0] 83 COL[7] 84 COL[6] 85 COL[5] 86 COL[4] 87 COL[3] 88 COL[2] 89 VDDIO 90 TCLK 91 COL[1] 92 COL[0] 93 BUZ 94 D[31] 95 D[30] 96 D[29] 97 D[28] 98 VSSIO 99 A[27]/DRA[0] 100 D[27] 101 A[26]/DRA[1] 102 D[26] 103 A[25]/DRA[2] 104 D[25] 105 HALFWORD 106 A[24]/DRA[3] 107 VDDIO 108 ...
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... Pad Gnd I/O ground I/O Data I/O I Battery changed sense input External power supply sense I input I Battery OK input I Power-on reset input Media change interrupt input / I internal ROM boot enable I User reset input Oscillator power in, 2 Main oscillator input O Main oscillator output Oscillator Ground EP7312 35 ...
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... EP7312 High-Performance, Low-Power System on Chip Pin Signal No. 161 WAKEUP 162 nPWRFL 163 A[6] 164 D[6] 165 A[5] 166 D[5] 167 VDDIO 168 VSSIO 169 A[4] 170 D[4] 171 A[3] 172 D[3] 173 A[2] 174 VSSIO 175 D[2] 176 A[1] 177 D[1] 178 A[0] 179 D[0] 180 VSSCORE 181 VDDCORE 182 VSSIO 183 VDDIO 184 CL[2] 185 ...
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... Input. Port A,B,D,E GPIOs default to input at nPOR and URESET conditions. DS508PP5 Table 20. 208-Pin LQFP Numeric Pin Listing (Continued) Reset † Strength State 1 High 1 High 1 High C opyright Cirrus Logic, Inc. 2003 © (All Rights Reserved) High-Performance, Low-Power System on Chip Type Description O Chip select 2 O Chip select 3 O Chip select 4 EP7312 37 ...
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... EP7312 High-Performance, Low-Power System on Chip 204-Ball TFBGA Package Characteristics TOP VIEW A1 CORNER SEATING PLANE Figure 17. 204-Ball TFBGA Package C opyright Cirrus Logic, Inc. 2003 © ...
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... BATOK GNDIO nBATCHG nMEDCHG/n nEXTPWR BROM D[7] D[8] A[10] D[12] A[11] D[13] A[14]/ D[14] DRA[13] VDDIO D[16] A[15]/ A[17]/ DRA[12] DRA[10] D[17] D[19] A[20]/ D[18] DRA[7] A[19]/ D[22] DRA[8] D[21] D[23] HALF D[24] WORD A[26]/ BUZ D[29] VDDIO VDDIO DRA[1] A[27]/ D[30] D[26] VDDIO DRA[0] A[25]/ D[31] D[28] D[27] DRA[2] EP7312 19 20 GNDIO A nURESET B nPOR C A[7] D D[9] E A[8] D[10] F A[9] D[11] G A[12] H A[13]/ J DRA[14] D[15] K A[16]/ L DRA[11] nTRST M A[18]/ N DRA[9] D[20] P A[21]/ R DRA6 A[22]/ T DRA5 A[23]/ U DRA4 A[24]/ V DRA3 D[25] W VDDIO ...
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... EP7312 High-Performance, Low-Power System on Chip 204-Ball TFBGA Ball Listing The list is ordered by ball location. Ball Location Name A1 VDDIO A2 EXPCLK A3 nCS[3] A4 nCS[1] A5 nMWE/nSDWE A6 SDQM[2] A7 nSDCS[1] A8 DD[2] A9 FRM A10 CL[1] A11 VSSCORE A12 D[1] A13 A[2] A14 D[4] A15 A[5] A16 nPWRFL A17 MOSCOUT A18 VSSIO A19 VSSIO ...
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... System byte address 1 Low I/O Data I/O 2 Low O System byte address 1 Low I/O Data I/O 1 Low O System byte address Oscillator ground PLL ground Oscillator power Oscillator power in, 2.5V Pad ground I/O ground I Battery ok input C opyright Cirrus Logic, Inc. 2003 © (All Rights Reserved) High-Performance, Low-Power System on Chip Description EP7312 41 ...
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... EP7312 High-Performance, Low-Power System on Chip Ball Location Name C20 nPOR D1 PB[7] D2 RXD[2] D3 VDDIO D18 VSSIO D19 nBATCHG D20 A[7] E1 PB[4] E2 TXD[2] E3 WRITE/nSDRAS E18 nMEDCHG/nBROM E19 nEXTPWR E20 D[9] F1 PB[3] F2 PB[6] F3 TDI F18 D[7] F19 A[8] F20 D[10] G1 PB[1] G2 PB[2] G3 PB[5] G18 D[8] G19 A[9] G20 D[11] H1 PA[7] H[2] TDO H[3] PB[0] H[18] A[10] H19 D[12] H20 A[12] J1 PA[4] 42 Table 21. 204-Ball TFBGA Ball Listing (Continued) Reset † ...
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... Data I/O 1 Low I/O Data I/O 1 Low O System byte address / SDRAM address I External interrupt I External interrupt input I UART 1 data carrier detect 1 Low I/O Data I/O 1 Low O System byte address / SDRAM address C opyright Cirrus Logic, Inc. 2003 © (All Rights Reserved) High-Performance, Low-Power System on Chip Description EP7312 43 ...
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... EP7312 High-Performance, Low-Power System on Chip Ball Location Name P20 D[20] R1 nEXTFIQ R2 PE[2]/CLKSEL R3 nTEST[0] R18 A[19]/DRA[8] R19 D[22] R20 A[21]/DRA[6] T1 PE[1]/BOOTSEL[1] T2 PE[0]/BOOTSEL[0] T3 nEINT[1] T18 D[21] T19 D[23] T20 A[22]/DRA[5] U1 VSSRTC U2 RTCOUT U3 RTCIN U18 HALFWORD U19 D[24] U20 A[23]/DRA[4] V1 VDDRTC V2 VSSIO V3 VSSIO V4 PD[7]/SDQM[1] V5 PD[4] V6 PD[2] V7 SSICLK V8 SSIRXDA V9 nADCCS V10 ...
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... GPIO port D 1 Low I/O GPIO port D / LED blinker output 1 Low O DAI/CODEC/SSI2 serial data output I SSI1 ADC serial input Core power Digital core power, 2.5V ‡ 2 I/O PWM drive output Input C opyright Cirrus Logic, Inc. 2003 © (All Rights Reserved) High-Performance, Low-Power System on Chip Description EP7312 45 ...
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... PBGA Package Characteristics Note: 1) For pin locations see Table 2) Dimensions are in millimeters (inches), and controlling dimension is millimeter 3) Before beginning any new EP7312 design, contact Cirrus Logic for the latest package information. 46 Table 21. 204-Ball TFBGA Ball Listing (Continued) Reset † Type ...
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... BOTTOM VIEW C opyright Cirrus Logic, Inc. 2003 © (All Rights Reserved) High-Performance, Low-Power System on Chip 0.85 (0.034) ±0.05 (.002) 0.40 (0.016) ±0.05 (.002) 30° TYP 2 Layer 0.36 (0.014) ±0.09 (0.004) SIDE VIEW Pin 1 Corner 17.00 (0.669) JEDEC #: MO-151 Ball Diameter: 0.50 mm ± 0. ¥ 17 ¥ 1.61 mm body EP7312 47 ...
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... EP7312 High-Performance, Low-Power System on Chip 256-Ball PBGA Pinout (Top View VDDIO nCS[4] nCS[1] SDCLK SDQM[3] nMOE/ B nCS[5] VDDIO nCS[3] VDDIO nSDCAS C VDDIO EXPCLK VSSIO VDDIO VSSIO WRITE/ D EXPRDY VSSIO VDDIO nCS[2] nSDRAS E RXD[2] PB[7] TDI WORD VSSIO RUN/ F PB[5] PB[3] VSSIO TXD[2] ...
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... Pad ground I/O ground Pad ground I/O ground Pad power Digital I/O power, 3.3 V Pad ground I/O ground Pad ground I/O ground Pad ground I/O ground Pad power Digital I/O power, 3.3 V Pad ground I/O ground C opyright Cirrus Logic, Inc. 2003 © (All Rights Reserved) High-Performance, Low-Power System on Chip Description EP7312 49 ...
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... EP7312 High-Performance, Low-Power System on Chip Ball Location Name Strength C14 VSSIO C15 nPOR Schmitt C16 nEXTPWR D1 WRITE/nSDRAS D2 EXPRDY D3 VSSIO D4 VDDIO D5 nCS[2] D6 nMWE/nSDWE D7 nSDCS[0] D8 CL[2] D9 VSSRTC D10 D[4] D11 nPWRFL D12 MOSCIN D13 VDDIO D14 VSSIO D15 D[7] D16 D[8] E1 RXD[2] E2 PB[7] E3 TDI with p/u* E4 WORD ...
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... Low I/O Data I/O ‡ 1 I/O GPIO port A Input ‡ 1 I/O GPIO port A Input Pad ground I/O ground ‡ 1 I/O GPIO port A Input ‡ 1 I/O GPIO port A Input 1 High O UART 1 transmit data out C opyright Cirrus Logic, Inc. 2003 © (All Rights Reserved) High-Performance, Low-Power System on Chip Description EP7312 51 ...
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... EP7312 High-Performance, Low-Power System on Chip Ball Location Name Strength J7 CTS J8 VSSRTC J9 VSSRTC J10 A[17]/DRA[10] J11 A[16]/DRA[11] J12 A[15]/DRA[12] J13 A[14]/DRA[13] J14 nTRST J15 D[16] J16 D[17] K1 LEDDRV K2 PHDIN K3 VSSIO K4 DCD K5 nTEST[1] With p/u* K6 EINT[3] K7 VSSRTC K8 ADCIN K9 COL[4] K10 TCLK K11 D[20] K12 D[19] K13 D[18] K14 VSSIO ...
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... Pad ground I/O ground 1 Low I/O Data I/O Pad power Digital I/O power, 3.3V I/O Real time clock oscillator input Pad power Digital I/O power, 3.3V 1 Low I/O GPIO port D 1 Low I/O GPIO port D C opyright Cirrus Logic, Inc. 2003 © (All Rights Reserved) High-Performance, Low-Power System on Chip Description EP7312 53 ...
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... EP7312 High-Performance, Low-Power System on Chip Ball Location Name Strength R5 SSITXDA R6 nADCCS R7 VDDIO R8 ADCOUT R9 COL[7] R10 COL[3] R11 COL[1] R12 D[30] R13 A[27]/DRA[0] R14 A[25]/DRA[2] R15 VDDIO R16 A[24]/DRA[3] T1 VDDRTC T2 PD[7]/SDQM[1] T3 PD[6]/SDQM[0] T4 PD[3] T5 SSICLK T6 SSIRXFR T7 VDDCORE T8 DRIVE[0] T9 FB[1] T10 COL[5] T11 VDDIO T12 BUZ ...
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... C opyright Cirrus Logic, Inc. 2003 © (All Rights Reserved) High-Performance, Low-Power System on Chip Type Position I/O 17 I/O 20 I/O 23 I/O 26 I/O 29 I/O 32 I/O 35 I/O 38 I/O 41 I/O 44 I/O 47 I/O 50 I/O 53 I/O 56 I I/O 80 I/O 83 I/O 86 I/O 89 I/O 92 I/O 95 EP7312 55 ...
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... EP7312 High-Performance, Low-Power System on Chip Table 23. JTAG Boundary Scan Signal Ordering (Continued) LQFP TFBGA Pin No 100 101 102 103 104 105 106 109 110 56 PBGA Signal ...
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... Type Position I/O 196 O 199 I/O 201 O 204 I/O 206 O 209 I/O 211 O 214 I/O 216 O 219 I/O 221 O 224 I/O 226 O 229 I/O 231 O 234 I/O 236 O 239 I/O 241 O 244 I/O 246 O 249 I/O 251 O 254 I/O 256 O 259 I/O 261 O 264 I/O 266 O 269 I/O 271 O 274 I/O 276 I 279 I 280 I 281 I 282 I 283 EP7312 57 ...
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... EP7312 High-Performance, Low-Power System on Chip Table 23. JTAG Boundary Scan Signal Ordering (Continued) LQFP TFBGA Pin No. 156 161 162 163 164 165 166 169 170 171 172 173 175 176 177 178 179 184 185 186 187 188 189 191 192 193 ...
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... See EP7312 Users’ Manual for pin naming / functionality. 2) For each pad, the JTAG connection ordering is input, output, then enable as applicable. DS508PP5 High-Performance, Low-Power System on Chip C opyright Cirrus Logic, Inc. 2003 © (All Rights Reserved) EP7312 59 ...
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... EP7312 High-Performance, Low-Power System on Chip CONVENTIONS This section presents acronyms, abbreviations, units of measurement, and conventions used in this data sheet. Acronyms and Abbreviations Table 24 lists abbreviations and acronyms used in this data sheet. Table 24. Acronyms and Abbreviations Acronym/ Abbreviation A/D analog-to-digital ADC analog-to-digital converter ...
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... Registers are referred to by acronym, with bits listed in brackets separated by a colon (:) (for example, CODR[7:0]), and are described in the EP7312 User’s Manual. The use of “TBD” indicates values that are “to be determined,” “n/a” designates “not available,” and “ ...
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... EP7312 High-Performance, Low-Power System on Chip Ordering Information The following EP7312 devices are available: — EP7312-CV — EP7312-IV — EP7312-CB — EP7312-CR — EP7312-CV-90 — EP7312-CB-90 — EP7312-CR-90 — EP7312-IB — EP7312-IR — EP7312-IV-90 — EP7312-IB-90 — EP7312-IR-90 Ordering Information Legend . EP7312 — CV —XX ...
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... This page intentionally blank. DS508PP5 High-Performance, Low-Power System on Chip C opyright Cirrus Logic, Inc. 2003 © (All Rights Reserved) EP7312 63 ...
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... EP7312 High-Performance, Low-Power System on Chip Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided " ...