HT83003 HOLTEK [Holtek Semiconductor Inc], HT83003 Datasheet - Page 16
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HT83003
Manufacturer Part Number
HT83003
Description
Q-Voice
Manufacturer
HOLTEK [Holtek Semiconductor Inc]
Datasheet
1.HT83003.pdf
(21 pages)
The TMR0C is the timer counter 0 control register, which
defines the timer counter 0 options. The timer counter 1
has the same options as the timer counter 0 and is de-
fined by TMR1C.
To enable the counting operation, the Timer ON bit
(TON; bit 4 of TMR0C/TMR1C) should be set to 1. The
overflow of the timer counter is one of the wake-up
sources. No matter what the operation mode is, writing a
0 to ET0I/ET1I can disable the corresponding interrupt
service.
The registers states are summarized in the following table.
Note:
Rev. 0.10
PC
MP0
ACC
TBLP
TBLH
WDTS
STATUS
INTC
TMR0
TMR0C
TMR1
TMR1C
LATCH0H
LATCH0M
LATCH0L
PA
PAC
PWMCR
PWMD
LATCHD
Register Reset (Power On)
u means unchanged ; x means unknown ;
0000 0111
1111 1111
1111 1111
-000 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
--00 xxxx
-00- 00-0
00-0 1---
00-0 1---
---- --xx
0000H
(Normal Operation)
WDT Time-out
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0111
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
1111 1111
1111 1111
uuuu uuuu
uuuu uuuu
-000 0000
--1u uuuu
-uu- uu-u
00-0 1---
00-0 1---
---- --uu
0000H
Timer Counter 0/1
Preliminary
Time Base
(Normal Operation)
16
RES Reset
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0111
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
1111 1111
1111 1111
uuuu uuuu
uuuu uuuu
-000 0000
--uu uuuu
-uu- uu-u
The TMR0/1 is internal clock source only. There is a
3-bit prescaler (TMRS2, TMRS1, TMRS0) which de-
fines different division ratio of TMR0/1 s clock source.
Time Base
The time base enables the counting operation by
INTC.1 (ETBI) bit. The overflow to interrupt as set
INTC.1. The time base is internal clock source only.
Time base of 1ms to overflow as system clock is 4MHz.
Time base of 0.5ms to overflow as system clock is
8MHz.
00-0 1---
00-0 1---
---- --uu
means undefined
0000H
RES Reset
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0111
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
1111 1111
1111 1111
uuuu uuuu
uuuu uuuu
-000 0000
--01 uuuu
-uu- uu-u
00-0 1---
00-0 1---
---- --uu
(HALT)
0000H
WDT Time-out
August 25, 2003
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
--11 uuuu
HT83XXX
-uu- uu-u
uu-u u---
uu-u u---
---- --uu
(HALT)
0000H