XC6109 TOREX [Torex Semiconductor], XC6109 Datasheet - Page 8

• Manufacturer Part Number: XC6109
• Description: Voltage Detector with External Delay Type Capacitor
• Manufacturer: TOREX [Torex Semiconductor]

XC6109
8/13
■OPERATIONAL EXPLANATION
●Release Delay Time Chart
Delay Capacitance [Cd]
① As an early state, the input voltage pin is applied sufficiently high voltage to the release voltage and the delay capacitance
② When the input pin voltage keeps dropping and becomes equal to the detect voltage (V
③ While the input pin voltage keeps below the detect voltage, and 0.7V or more, the delay capacitance is discharged to the
④ While the input pin voltage drops to 0.7V or less and it increases again to 0.7V or more, the output voltage may not be
⑤ While the input pin voltage increases more than 0.7V and it reaches to the release voltage level (V
⑥ When the input pin voltage continues to increase more than 0.7V up to the release voltage level (= V
⑦ While the input pin voltage becomes equal to the release voltage or higher and keeps the detect voltage or higher, the
⑧ While the input pin voltage is higher than the detect voltage (V
The release delay time can also be briefly calculated with the formula (2) because the delay resistance is 2.0MΩ(TYP.) and
As an example, presuming that the delay capacitance is 0.68μF, TDR is :
the delay capacitance pin threshold voltage is V
* Note that the release delay time may remarkably be short when the delay capacitance is not discharged to the ground
A typical circuit example is shown in Figure 1, and the timing chart of Figure 1 is shown in Figure 2 on the next page.
(=V
(Cd) is charged to the input pin voltage. While the input pin voltage (V
(V
the delay capacitance discharge is turned ON, and starts to discharge the delay capacitance. For the internal circuit,
which uses the delay capacitance pin as power input, the reference voltage operates as a comparator of V
output voltage changes into the “Low” level (≦V
from V
ground voltage (=V
able to maintain the “Low” level. Such an operation is called “Unspecified Operation”, and voltage which occurs at the
output pin voltage is defined as unstable operating voltage (V
output voltage (V
transistor for the delay capacitance discharge will be turned OFF, and the delay capacitance will be started discharging
via a delay resistor (Rdelay). The internal circuit, which uses the delay capacitance pin as power input, will operate as a
hysteresis comparator (Rise Logic Threshold: V
keeps higher than the detect voltage (V
delay capacitance (Cd) will be charged up to the input pin voltage. When the delay capacitance pin voltage (V
reaches to the delay capacitance pin threshold voltage (V
T
connected: T
“High”(=V
DR
DF
SS
0.022
0.047
(μF)
0.01
0.22
0.47
) (V
is defined as time which ranges from V
0.1
) level because time described in ③ is short.
1
IN
IN
=V
IN
> V
) level.
DF
Series
DR0
DF
to the V
OUT)
). T
), the output voltage (V
SS
) level. Then, the output voltage (V
DR
maintains the “Low” level.
OUT
Release Delay Time [T
can be given by the formula (1).
of “Low” level (especially, when the Cd pin is not connected: T
T
* In = a natural logarithm
DR
=
－
1380
13.8
30.4
64.9
IN
138
304
649
(ms)
OUT
Rdelay
2.0e6
> V
IN
) keeps the “High” level (=V
TDR = 2.0e6
IN /2
DF
=V
×
DR
×
TLH
).
IN
DF
0.68e
Cd
(TYP.)
] (TYP.)
×0.1). The detect delay time (T
=V
+V
×
TCD
HYS
In (1
－
×
6
OUT)
TCD
×
, Fall Logic Threshold: V
to the V
Cd
－
0.69 = 938 (ms)
UNS)
V
), the output voltage changes into the “High” (=V
×
maintains the “Low” level.
TCD
0.69…(2)
Release Delay Time [T
IN
.
OUT
> V
/ V
IN
IN
DF
of “High” level (especially when the Cd pin is not
) +T
IN
).
), therefore, the output voltage maintains the
) starts dropping to reach the detect voltage
DR0
1100 ~ 1660
24.3 ~ 36.4
51.9 ~ 77.8
11.0 ~ 16.6
110 ~ 166
519 ~ 778
243~ 364
(ms)
…(1)
THL
DF
DR
) is defined as time which ranges
=V
IN
] (MIN. ~ MAX.)
DF0
SS
= V
).
) while the input pin voltage
DF
), an N-ch transistor for
IN
DF
＜V
+ V
DF
HYS
+V
IN
HYS
), the N-ch
, and the
IN
) level.
), the
CD
)