S-814 SII [Seiko Instruments Inc], S-814 Datasheet - Page 12

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S-814

Manufacturer Part Number
S-814
Description
LOW DROPOUT CMOS VOLTAGE REGULATOR
Manufacturer
SII [Seiko Instruments Inc]
Datasheet

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12
LOW DROPOUT CMOS VOLTAGE REGULATOR
S-814 Series
1. Basic operation
2. Output transistor
Operation
Figure 12 shows the block diagram of the S-814 Series.
The error amplifier compares a reference voltage V
feedback resistors R
certain output voltage free of any fluctuations of input voltage and temperature.
The S-814 Series uses a low on-resistance Pch MOS FET as the output transistor.
Be sure that V
inverse current flowing from VOUT pin through a parasitic diode to VIN pin.
*1. Parasitic diode
Current source
OUT
VSS
VIN
does not exceed V
s
and R
Reference voltage
V
f
ref
. It supplies the output transistor with the gate voltage, necessary to ensure
circuit
Error amplifier
IN
Seiko Instruments Inc.
+0.3 V to prevent the voltage regulator from being broken due to
+
Figure 12
ref
with part of the output voltage divided by the
R
Rs
f
*1
VOUT
Rev.2.1
_00

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