AK4358_06 AKM [Asahi Kasei Microsystems], AK4358_06 Datasheet - Page 21

• Manufacturer Part Number: AK4358_06
• Description: 192kHz 24-Bit 8ch DAC with DSD Input
• Manufacturer: AKM [Asahi Kasei Microsystems]

ASAHI KASEI
When the input data at all channels are continuously zeros for 8192 LRCK cycles, the AK4358 has Zero Detection like
Table 16. DZF pin immediately goes to “L” if input data of each channel is not zero after going DZF “H”. If RSTN bit is
“0”, DZF pin goes to “H”. DZF pin goes to “L” at 4~5LRCK if input data of each channel is not zero after RSTN bit
returns to “1”. Zero detect function can be disabled by DZFE bit. In this case, all DZF pins are always “L”. When one of
PW1-4 bit is set to “0”, the input data of DAC that the PW bit is set to “0” should be zero in order to enable zero detection
of the other channels. When all PW1-4 bits are set to “0”, DZF pin fixes “L”. DZFB bit can invert the polarity of DZF pin.
Soft mute operation is performed at digital domain. When the SMUTE bit goes to “1”, the output signal is attenuated by
- ∞ during ATT_DATA × ATT transition time (Table 15) from the current ATT level. When the SMUTE bit is returned to
“0”, the mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATA × ATT
transition time. If the soft mute is cancelled before attenuating to - ∞ after starting the operation, the attenuation is
discontinued and returned to ATT level by the same cycle. The soft mute is effective for changing the signal source
without stopping the signal transmission.
Notes:
MS0203-E-01
Zero Detection
Soft Mute Operation
(2) The analog output corresponding to the digital input has a group delay, GD.
(4) When the input data at each channel is continuously zeros for 8192 LRCK cycles, DZF pin of each channel goes to
(1) ATT_DATA × ATT transition time (Table 15). For example, in Normal Speed Mode, this time is 1792LRCK cycles
(3) If the soft mute is cancelled before attenuating to - ∞ after starting the operation, the attenuation is discontinued and
(1792/fs) at ATT_DATA=128.
returned to ATT level by the same cycle.
“H”. DZF pin immediately goes to “L” if input data are not zero after going DZF “H”.
SMUTE bit
Attenuation
AOUT
DZF pin
DZF Pin
DZF1
DZF2
DZF3
ATT Level
-∞
ANDed output of zero detection flag of each channel set to “1” in 0DH register
ANDed output of zero detection flag of each channel set to “1” in 0EH register
ANDed output of zero detection flag of each channel set to “1” in 0FH register
Figure 14. Soft Mute and Zero Detection
(1)
Table 16. DZF pins Operation
8192/fs
(4)
- 21 -
GD
(2)
Operations
(1)
GD
(3)
[AK4358]
2006/02