AK4392 AKM [Asahi Kasei Microsystems], AK4392 Datasheet - Page 29

• Manufacturer Part Number: AK4392
• Description: High Performance 120dB Premium 32-Bit DAC
• Manufacturer: AKM [Asahi Kasei Microsystems]

(2) RESET by MCLK or LRCK/WCK Stop
The AK4392 is automatically placed in reset state when MCLK or LRCK is stopped during PDM mode (RSTN pin
=“H”), and the analog outputs are floating (Hi-Z). When MCLK and LRCK are input again, the AK4392 exits reset state
and starts the operation. Zero detect function is disable when MCLK or LRCK is stopped. In DSD mode the AK4392 is in
reset state when MCLK is stopped, and it is in reset state when MCLK and WCK are stopped in external digital filter
mode.
Internal
D/A In
D/A Out
Clock In
MCLK, BICK, LRCK
Notes:
MS1045-E-02
RSTB pin
AVDD pin
DVDD pin
External
MUTE
(Digital)
(Analog)
State
(1) After AVDD and DVDD are powered-up, the PDN pin should be “L” for 150ns.
(2) The analog output corresponding to digital input has group delay (GD).
(3) The digital data can be stopped. Click noise after MCLK, BICK and LRCK are input again can be reduced by
(4) Click noise occurs within 3 ~ 4LRCK cycles from the riding edge (“↑”) of the PDN pin or MCLK inputs. This
(5) Clocks (MCLK, BICK, LRCK) can be stopped in the reset state (MCLK or LRCK is stopped).
(6) Mute the analog output externally if click noise (4) influences system applications. The timing example is shown
inputting “0” data during this period.
noise occurs even when “0” data is input.
in this figure.
Power-down
Power-down
(1)
Hi-Z
(6)
(4)
Normal O peration
Figure 15. Reset Sequence Example 2
GD
(2)
- 29 -
(6)
MCLK, BICK, LRCK Stop
(4)
Digital Circuit P ower-down
(5)
(3)
(5)
(4)
(6)
Normal Operation
GD
(2)
[AK4392]
2009/04