XR16C2450IJ EXAR [Exar Corporation], XR16C2450IJ Datasheet - Page 15

• Manufacturer Part Number: XR16C2450IJ
• Description: 2.97V TO 5.5V DUART
• Manufacturer: EXAR [Exar Corporation]

xr
REV. 1.0.0
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ISR[0]: Interrupt Status
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ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See
ISR[7:4]: Reserved
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
4.5
4.4.1
4.4.2
LSR is by any of the LSR bits 1, 2, 3 and 4.
RXRDY is by data byte received in RHR.
TXRDY is by THR empty.
MSR is by any of the MSR bits 0, 1, 2 and 3.
LSR interrupt is cleared by a read to the LSR register.
RXRDY interrupt is cleared by reading data out of RHR.
TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
MSR interrupt is cleared by a read to the MSR register.
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending (default condition).
P
RIORITY
Line Control Register (LCR) - Read/Write
1
2
3
4
-
Interrupt Generation:
Interrupt Clearing:
L
EVEL
B
IT
0
0
0
0
0
-3
ISR R
T
B
ABLE
EGISTER
IT
1
1
0
0
0
BIT-1
-2
0
0
1
1
6: I
S
B
NTERRUPT
TATUS
IT
1
0
1
0
0
-1
BIT-0
B
0
1
0
1
ITS
B
IT
S
0
0
0
0
1
-0
OURCE AND
15
LSR (Receiver Line Status Register)
RXRDY (Received Data Ready)
TXRDY (Transmit Ready)
MSR (Modem Status Register)
None (default)
W
5 (default)
ORD LENGTH
P
RIORITY
6
7
8
S
L
OURCE OF INTERRUPT
EVEL
Table
2.97V TO 5.5V DUART
6).
XR16C2450