XR16C850CJ EXAR [Exar Corporation], XR16C850CJ Datasheet - Page 28

• Manufacturer Part Number: XR16C850CJ
• Manufacturer: EXAR [Exar Corporation]

FCR BIT-2:
Logic 0 = No FIFO transmit reset. (normal default
condition)
Logic 1 = Clears the FIFO counter and resets the
pointers logic (the transmit shift register is not cleared
or altered). This bit will return to a logic 0 after clearing
the FIFO.
FCR BIT-3:
Logic 0 = Set DMA mode “0”. (normal default condition)
Logic 1 = Set DMA mode “1.”
Transmit operation in mode “0”:
When the 850 is in the ST16C450 mode (FIFOs dis-
abled, FCR bit-0 = logic 0) or in the FIFO mode (FIFOs
enabled, FCR bit-0 = logic 1, FCR bit-3 = logic 0) and
when there are no characters in the transmit FIFO or
transmit holding register, the -TXRDY pin will be a logic
0. Once active the -TXRDY pin will go to a logic 1 after
the first character is loaded into the transmit holding
register.
Receive operation in mode “0”:
When the 850 is in mode “0” (FCR bit-0 = logic 0) or in
the FIFO mode (FCR bit-0 = logic 1, FCR bit-3 = logic
0) and there is at least one character in the receive FIFO,
the -RXRDY pin will be a logic 0. Once active the -
RXRDY pin will go to a logic 1 when there are no more
characters in the receiver.
Transmit operation in mode “1”:
When the 850 is in FIFO mode ( FCR bit-0 = logic 1, FCR
bit-3 = logic 1 ), the -TXRDY pin will be a logic 1 when
the transmit FIFO is completely full. It will be a logic 0
if one or more FIFO locations are empty.
Receive operation in mode “1”:
When the 850 is in FIFO mode (FCR bit-0 = logic 1, FCR
bit-3 = logic 1) and the trigger level has been reached,
or a Receive Time Out has occurred, the -RXRDY pin will
go to a logic 0. Once activated, it will go to a logic 1 after
there are no more characters in the FIFO.
FCR BIT 4-5: (logic 0 or cleared is the default condition,
TX trigger level = none)
The XR16C850 provides 4 user selectable trigger levels,
The FCTR Bits 4-5 selects one of the following tables.
These bits are used to set the trigger level for the
transmit FIFO interrupt. The XR16C850 will issue a
XR16C850
Rev. 1.20
28
transmit empty interrupt when the number of characters
in FIFO drops below the selected trigger level.
TRIGGER TABLE-A (Transmit)
“Default setting after reset, ST16C550 mode”
TRIGGER TABLE-B (Transmit)
TRIGGER TABLE-C (Transmit)
TRIGGER TABLE-D (Transmit)
FCR BIT 6-7: (logic 0 or cleared is the default condition,
RX trigger level =8)
These bits are used to set the trigger level for the
receiver FIFO interrupt. The interrupt will trigger again
when RX data is unloaded below the threshold and
incoming data fills it back up to the trigger level. The
FCTR Bits 4-5 selects one of the following tables.
BIT-5
BIT-5
BIT-5
BIT-5
X
0
0
1
1
0
0
1
1
X
BIT-4
BIT-4
BIT-4
BIT-4
X
0
1
0
1
0
1
0
1
X
User programmable
FIFO trigger level
FIFO trigger level
FIFO trigger level
FIFO trigger level
Trigger levels
None
16
24
30
16
32
56
8
8