XR16C854CV EXAR [Exar Corporation], XR16C854CV Datasheet - Page 31
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XR16C854CV
Manufacturer Part Number
XR16C854CV
Description
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
Manufacturer
EXAR [Exar Corporation]
Datasheet
1.XR16C854CV.pdf
(54 pages)
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xr
REV. 3.0.1
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See
•
•
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format.
•
•
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR BIT-5 selects the forced parity format.
•
•
•
LCR[6]: Transmit Break Enable
When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space’, logic 0, state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.
•
•
LCR[7]: Baud Rate Divisors Enable
•
•
Logic 0 = No parity.
Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format (default).
Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format.
LCR BIT-5 = logic 0, parity is not forced (default).
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive
data.
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive
data.
Logic 0 = No TX break condition (default).
Logic 1 = Forces the transmitter output (TX) to a “space”, logic 0, for alerting the remote receiver of a line
break condition.
Logic 0 = Data registers are selected (default).
Logic 1 = Divisor latch registers are selected.
Table 12
LCR B
X
0
0
1
1
IT
for parity selection summary below.
-5
LCR B
X
0
1
0
1
T
ABLE
IT
-4
12: P
LCR B
ARITY SELECTION
31
0
1
1
1
1
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
IT
-3
Forced parity to space, “0”
Force parity to mark, “1”
P
ARITY SELECTION
Even parity
Odd parity
No parity
XR16C854/854D