XR16L2751CM EXAR [Exar Corporation], XR16L2751CM Datasheet - Page 30

no-image

XR16L2751CM

Manufacturer Part Number
XR16L2751CM
Description
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
Manufacturer
EXAR [Exar Corporation]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XR16L2751CM
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
Part Number:
XR16L2751CM-F
Manufacturer:
EXAR
Quantity:
1 597
Part Number:
XR16L2751CM-F
Manufacturer:
Exar Corporation
Quantity:
10 000
Part Number:
XR16L2751CM-F
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
Company:
Part Number:
XR16L2751CM-F
Quantity:
263
Company:
Part Number:
XR16L2751CM-F
Quantity:
250
Company:
Part Number:
XR16L2751CM-F
Quantity:
157
Part Number:
XR16L2751CMTR-F
Manufacturer:
Exar Corporation
Quantity:
10 000
Part Number:
XR16L2751CMTR-F
Manufacturer:
EXAR
Quantity:
8 000
Company:
Part Number:
XR16L2751CMTR-F
Quantity:
958
áç
áç
áç
áç
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in conjunction with the programmed word length.
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format.
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR BIT-5 selects the forced parity format.
Logic 0 = No parity.
Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format (default).
Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format.
LCR BIT-5 = logic 0, parity is not forced (default).
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive
data.
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive
data.
Table 12
LCR B
for parity selection summary below.
BIT-2
X
0
0
1
1
0
1
1
IT
-5 LCR B
T
ABLE
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
X
0
1
0
1
LENGTH
5,6,7,8
W
IT
6,7,8
-4 LCR B
ORD
12: P
5
ARITY SELECTION
30
0
1
1
1
1
IT
-3
S
Force parity to mark,
TOP BIT LENGTH
(B
P
1 (default)
Forced parity to
ARITY SELECTION
IT TIME
1-1/2
Even parity
Odd parity
space, “0”
No parity
2
“1”
(
S
))
XR16L2751
REV. 1.0.0

Related parts for XR16L2751CM