XR20M1170IL16 EXAR [Exar Corporation], XR20M1170IL16 Datasheet - Page 37

• Manufacturer Part Number: XR20M1170IL16
• Description: I2C/SPI UART WITH 64-BYTE FIFO
• Manufacturer: EXAR [Exar Corporation]

REV. 1.0.0
This register is used to program the direction of the GPIO pins. Bit-7 to bit-0 controls GPIO7 to GPIO0.
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This register reports the state of all GPIO pins during a read and writes to any GPIO that is an output.
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This register enables the interrupt for the GPIO pins. The interrupts for GPIO[7:4] are only enabled if
IOControl[1] = 0. If IOControl[0] = 1 (GPIO pins are selected as modem IOs) , then IOIntEna[7:4] will have no
effect on GPIO[7:4].
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IOControl[7:4]: Reserved
IOControl[3]: UART Software Reset
Writing a logic 1 to this bit will reset the device. Once the device is reset, this bit will automatically be set to a
logic 0.
IOControl[2]: Reserved
IOControl[1]: GPIO[7:4] or Modem IO Select
This bit controls whether GPIO[7:4] behave as GPIO pins or as modem IO pins (RI#, CD#, DTR#, DSR#)
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IOControl[0]: IO Latch
This bit enable/disable GPIO inputs latching.
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EFCR[7]: IrDA mode
This bit selects between the slow and fast IrDA modes. See
complete details.
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4.15
4.16
4.17
4.18
4.19
Logic 0 = set GPIO pin as input
Logic 1 = set GPIO pin as output
Logic 0 = set output pin LOW
Logic 1 = set output pin HIGH
Logic 0 = a change in the input pin will not generate an interrupt
Logic 1 = a change in the input will generate an interrupt
Logic 0 = GPIO[7:4] behave as GPIO pins
Logic 1 = GPIO[7:4] behave as RI#, CD#, DTR#, DSR#
Logic 0 = GPIO input values are not latched. A change in any GPIO input generates an interrupt. A read of
the IOState register clears the interrupt. If the input goes back to its initial logic state before the input register
is read, then the interrupt is cleared.
Logic 1 = GPIO input values are latched. A change in the GPIO input generates an interrupt and the input
logic value is loaded in the bit of the corresponding input state register (IOState). A read of the IOState
register clears the interrupt. If the input pin goes back to its initial logic state before the interrupt register is
read, then the interrupt is not cleared and the corresponding bit of the IOState register keeps the logic value
that generated the interrupt.
Logic 0 = IrDA version 1.0, 3/16 pulse ratio, data rate up to 115.2 Kbps
Logic 1 = IrDA version 1.1, 1/4 pulse ratio, data rate up to 1.152 Mbps
GPIO Direction Register (IODir) - Read/Write
GPIO State Register (IOState) = Read/Write
GPIO Interrupt Enable Register (IOIntEna) - Read/Write
GPIO Control Register (IOControl) - Read/Write
Extra Features Control Register (EFCR) - Read/Write
37
“Section 2.15, Infrared Mode” on page 21
I2C/SPI UART WITH 64-BYTE FIFO
XR20M1170
for