XR20V2172IL64 EXAR [Exar Corporation], XR20V2172IL64 Datasheet - Page 30

• Manufacturer Part Number: XR20V2172IL64
• Description: TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
• Manufacturer: EXAR [Exar Corporation]

XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
MCR[2]: OP1# / TCR and TLR Enable
OP1# is not available as an output pin on the V2172. But it is available for use during Internal Loopback Mode
(MCR[4] = 1). In the Internal Loopback Mode, this bit is used to write the state of the modem RI# interface
signal.
This bit is also used to select between the MSR and TCR registers at address offset 0x6 and the SPR and TLR
registers at address offset 0x7.
MCR[3]: OP2# Output / INT Output Enable
This bit enables or disables the operation of INT, interrupt output. If INT output is not used, OP2# can be used
as a general purpose output.
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•
MCR[4]: Internal Loopback Enable
•
•
MCR[5]: Xon-Any Enable (requires EFR bit-4=1 to write to this bit)
•
•
MCR[6]: Reserved
MCR[7]: Clock Prescaler Select (requires EFR bit-4=1 to write to this bit)
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•
Logic 0 = INT (A-B) outputs disabled (three state mode) and OP2# output set HIGH(default).
Logic 1 = INT (A-B) outputs enabled (active mode) and OP2# output set LOW.
Logic 0 = Disable loopback mode (default).
Logic 1 = Enable local loopback mode, see loopback section and
Logic 0 = Disable Xon-Any function (default).
Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation.
The RX character will be loaded into the RX FIFO, unless the RX character is an Xon or Xoff character and
the V2172 is programmed to use the Xon/Xoff flow control.
Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable
Baud Rate Generator without further modification, i.e., divide by one (default).
Logic 1 = Divide by four. The prescaler divides the input clock from the crystal or external clock by four and
feeds it to the Programmable Baud Rate Generator, hence, data rates become one forth.
EFR[4]
EFR[4] MCR[2] Register at Address Offset 0x6
0
1
1
0
1
1
Table 12
T
T
ABLE
ABLE
MCR[2] Register at Address Offset 0x7
X
0
1
X
0
1
12: R
13: R
and
Modem Status Register (MSR)
Modem Status Register (MSR)
Trigger Control Register (TCR)
Scratchpad Register (SPR)
Scratchpad Register (SPR)
Trigger Level Register (TLR)
EGISTER AT
EGISTER AT
PRELIMINARY
Table 13
30
below shows how these registers are accessed.
A
A
DDRESS
DDRESS
O
O
FFSET
FFSET
Figure
0
0
14.
X
X
6
7
REV. P1.0.1