XR16M2752IJ44 EXAR [Exar Corporation], XR16M2752IJ44 Datasheet - Page 26
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XR16M2752IJ44
Manufacturer Part Number
XR16M2752IJ44
Description
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
Manufacturer
EXAR [Exar Corporation]
Datasheet
1.XR16M2752IJ44.pdf
(52 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XR16M2752IJ44-F
Manufacturer:
Exar Corporation
Quantity:
10 000
XR16M2752
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
]
ISR[0]: Interrupt Status
•
•
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source
ISR[4]: Xoff or Special Character Interrupt Status (requires EFR bit-4=1)
This bit is enabled when IER[5] = 1. ISR bit-4 indicates that the receiver detected a data match of the Xoff
character(s) or special character (XOFF2).
ISR[5]: RTS#/CTS# Interrupt Status (requires EFR bit-4=1)
This bit is enabled when IER[7] = 1 or IER[6] = 1. ISR bit-5 indicates that the CTS# or RTS# has been de-
asserted.
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA, and FIFO modes are defined as follows:
FCR[0]: TX and RX FIFO Enable
•
•
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
•
•
4.5
P
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending (default condition).
Logic 0 = Disable the transmit and receive FIFO (default).
Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
Logic 0 = No receive FIFO reset (default)
Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
RIORITY
L
EVEL
1
2
3
4
5
6
7
-
FIFO Control Register (FCR) - Write-Only
B
IT
0
0
0
0
0
0
1
0
-5
B
IT
0
0
0
0
0
1
0
0
-4
ISR R
B
EGISTER
IT
T
0
1
0
0
0
0
0
0
ABLE
-3
B
9: I
S
IT
TATUS
1
1
1
0
0
0
0
0
-2
NTERRUPT
B
B
ITS
IT
1
0
0
1
0
0
0
0
-1
S
OURCE AND
26
B
IT
0
0
0
0
0
0
0
1
-0
LSR (Receiver Line Status Register)
RXRDY (Receive Data Time-out)
RXRDY (Received Data Ready)
TXRDY (Transmit Ready)
MSR (Modem Status Register)
RXRDY (Received Xoff or Special character)
CTS#, RTS# change of state
None (default)
P
RIORITY
L
EVEL
S
OURCE OF INTERRUPT
REV. P1.0.0
Table
9).