78M6631-IM/F MAXIM [Maxim Integrated Products], 78M6631-IM/F Datasheet - Page 13

• Manufacturer Part Number: 78M6631-IM/F
• Description: 3-Phase Power-Measurement IC
• Manufacturer: MAXIM [Maxim Integrated Products]

Since the addresses are in 16-bit format, any type of XRAM data can be accessed: CE, MPU, or IORAM
but not SFRs or the 80515-internal register bank.
1.19 Test Port
One out of 16 digital or eight analog signals can be selected to be output on the TMUXOUT pin. Refer to
the 78M6631 Programmer’s Reference Manual for more information regarding the use of TMUXOUT.
1.20 UART
The 78M6631 includes one UART (UART0) that can be programmed to communicate with a variety of
external devices. The UART is a dedicated 2-wire serial interfaces (no hardware flow
control/handshaking), which can communicate at rates up to 38,400 bps. All UART transfers are
programmable for parity enable, parity, 2 stop bits/1 stop bit and XON/XOFF options for variable
communication baud rates from 300 to 38,400 bps. Refer to the 78M6631 Programmer’s Reference
Manual for more information regarding the use of the UART resources.
Rev 1
11xx xxxx ADDR D0 ... DN
1100 0000 ADDR D0 ... DN
10xx xxxx ADDR D0 ... DN
1000 0000 ADDR D0 ... DN
CMD
SERIAL READ
SERIAL WRITE
(From 6531)
(From 6531)
(From Host)
(From Host)
PSDO
PSDO
PCSZ
PSCK
PCSZ
PSCK
PSDI
PSDI
Command
ADDR D0 ... DN
x
x
C7
C7
0
0
Figure 4: SPI Slave Port: Typical Read and Write Operations
C6
C6
8 bit CMD
8 bit CMD
C5
C5
HI Z
Table 1: SPI Command Description
Output data on PSDO is read from RAM starting with byte at ADDR.
ADDR auto increments until PCSZ is raised.
MPU SPI interrupt is generated.
Output data on PSDO is read from RAM starting with byte at ADDR.
ADDR auto increments until PCSZ is raised.
No MPU SPI interrupt is generated.
Input data on PSDI is written to RAM starting with byte at ADDR.
ADDR auto increments until PCSZ is raised.
MPU SPI interrupt is generated.
Input data on PSDI is written to RAM starting with byte at ADDR.
ADDR auto increments until PCSZ is raised.
No MPU SPI interrupt is generated.
CMD and ADDR are available to the CPU in IORAM.
D0… DN are ignored.
MPU SPI interrupt is generated.
C0
C0
7
7
A15
A15
8
8
A14
A14
16 bit Address
16 bit Address
A1
A1
HI Z
23
A0
23
A0
D7
D7
24
24
x
Description
D6
D6
DATA[ADDR]
DATA[ADDR]
D1
D1
31
31
D0
D0
D7
D7
32
32
Extended Read . . .
Extended Write . . .
D6
D6
DATA[ADDR+1]
DATA[ADDR+1]
D1
D1
D0
D0
39
39
x
13