SPEAR-09-H122_08 STMICROELECTRONICS [STMicroelectronics], SPEAR-09-H122_08 Datasheet
SPEAR-09-H122_08
Related parts for SPEAR-09-H122_08
SPEAR-09-H122_08 Summary of contents
Page 1
... The device integrates an ARM 926 core with a large set of proven IPs and a big configurable logic block that allow very fast customization of unique and/or proprietary solution. The SPEAR-09-H122 is designed for the - °C ambient temperature range. Package PBGA420(23x23x1.81mm) Rev 2 SPEAR-09-H122 SPEAr™ ...
Page 2
... ML1 multi layer CPU subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.6 ICM3 - basic subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4 Main blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1 7.1 CPU subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1.1 4.1.2 4.2 Clock and reset system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.3 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.3.1 4.3.2 4.4 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.4.1 4.4.2 2/40 USB 2.0 transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SSTL_2/SSTL_18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 CPU ARM 926EJ Crystal connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Crystal equivalent model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 RTC crystal connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 RTC crystal equivalent model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 SPEAR-09-H122 ...
Page 3
... SPEAR-09-H122 4.5 Ethernet controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.6 USB2 host controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.7 USB2 device controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.8 Low jitter PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.9 Reconfigurable logic array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.9.1 4.9.2 4.9.3 4.9.4 4.10 Other interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.10.1 4.10.2 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3 General purpose I/O characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.4 LVDS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.5 DDR I & DDR II pads electrical characteristics . . . . . . . . . . . . . . . . . . . . 36 6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7 Revision history ...
Page 4
... Low voltage TTL DC output specification (3V<vdde3V3<3.6V Table 16. Pull-up and pull-down characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 17. Driver specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 18. AC output specification (2.2V<vdde2v5<2.7V Table 19. Receiver specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 20. DC characteristics Table 21. Driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 22. On die termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 23. Reference voltage Table 24. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4/40 SPEAR-09-H122 ...
Page 5
... SPEAR-09-H122 List of figures Figure 1. Main SPEAr Head600 functional interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 3. Crystal connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 4. Crystal equivalent model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 5. RTC crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 6. RTC crystal equivalent model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 7. Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 8. PBGA420 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 List of figures ...
Page 6
... Reference documentation Reference documentation 1. ARM926EJ-S - technical reference manual 2. AMBA 2.0 specification 3. EIA/JESD8-9 specification 4. USB2.0 specification 5. OHCI specification 6. EHCI specification 7. USB specification 8. IEEE 802.3 specification bus specification 6/40 SPEAR-09-H122 ...
Page 7
... SPEAR-09-H122 1 Product overview An outline picture of the main SPEAr Head600 functional interfaces is shown in Figure 1. Main SPEAr Head600 functional interfaces 1.1 Features The following main functionalities are implemented in the SPEAr Head600 SoC device: ● ARM926EJ-S core @333 MHz, 16 Kbyte-I/D cache, configurable TMC-I/D size, MMU, TLB, JTAG and ETM trace module (multiplexed interfaces) ● ...
Page 8
... Internal memory pool (128 Kbyte) full configurable – external/internal source clock (some of these programmable) – Three memory path toward the SDRAM controller to ensure a good bandwidth ● Architecture easily extensible ● External memory bandwidth of each master tuneable to meet the target performances of different applications 8/40 SPEAR-09-H122 ...
Page 9
... SPEAR-09-H122 1.3 Block diagram Figure 2. Block diagram SPEAr Head600 Configurable Cell Array Subsystem SRAM SRAM 32KB 32KB Cell Array (Applic. configurable) SRAM SRAM 32KB 32KB ARM Subsystem CPU1 ARM926EJS APB Tmr 16kI/16kD Coproces. Int GPIO Cache ctr Tcm -I Multi-layer Bus Interconnection Matrix ...
Page 10
... Input Test clock D16 Input Test data input D15 Input Test mode select P4 I/O Programmable logic I/O SPEAR-09-H122 6, here follows the pin list, sorted by Pin type Analog buffer 2.5 V tolerant TTL input buffer, 3.3 V tolerant, PD TTL Schmitt trigger input buffer, 3.3 V tolerant, PU TTL output buffer, 3 ...
Page 11
... SPEAR-09-H122 Table 2. Pin description by functional group (continued) Group Signal name PL_GPIO_1 PL_GPIO_2 PL_GPIO_3 PL_GPIO_4 PL_GPIO_5 PL_GPIO_6 PL_GPIO_7 PL_GPIO_8 PL_GPIO_9 PL_GPIO_10 PL_GPIO_11 PL_GPIO_12 PL_GPIO_13 PL_GPIO_14 PL_GPIO_15 PL_GPIO_16 PL_GPIO_17 PL PL_GPIO_18 PL_GPIO_19 PL_GPIO_20 PL_GPIO_21 PL_GPIO_22 PL_GPIO_23 PL_GPIO_24 PL_GPIO_25 PL_GPIO_26 PL_GPIO_27 PL_GPIO_28 PL_GPIO_29 PL_GPIO_30 ...
Page 12
... PL_GPIO_62 PL_GPIO_63 PL_GPIO_64 PL_GPIO_65 PL_GPIO_66 PL_GPIO_67 PL_GPIO_68 PL_GPIO_69 PL_GPIO_70 12/40 Ball Direction Function I/O Programmable logic I SPEAR-09-H122 Pin type TTL BIDIR buffer, 3.3 V capable 3.3 V tolerant, PU ...
Page 13
... SPEAR-09-H122 Table 2. Pin description by functional group (continued) Group Signal name PL_GPIO_71 PL_GPIO_72 PL_GPIO_73 PL_GPIO_74 PL_GPIO_75 PL_GPIO_76 PL_GPIO_77 PL_GPIO_78 PL PL_GPIO_79 PL_GPIO_80 PL_GPIO_81 PL_GPIO_82 PL_GPIO_83 PL_CLK_1 PL_CLK_2 PL_CLK_3 PL_CLK_4 GMII_TXCLK GMII_TXCLK125 MII_TXCLK TXD_0 TXD_1 TXD_2 TXD_3 GMII_TXD_4 Ethernet GMII_TXD_5 GMII_TXD_6 GMII_TXD_7 TX_ER ...
Page 14
... Y20 Y21 Y22 W22 W21 W20 Output LCD data V20 V21 V22 U22 U21 SPEAR-09-H122 Pin type TTL Input buffer 3.3 V tolerant, PD TTL BIDIR buffer 3.3 V capable 3.3 V tolerant, PD TTL Input buffer 3.3 V tolerant, PD TTL BIDIR buffer 3.3 V capable 3.3 V tolerant, PD TTL output buffer 3 ...
Page 15
... SPEAR-09-H122 Table 2. Pin description by functional group (continued) Group Signal name CLD_11 CLD_12 CLD_13 CLD_14 CLD_15 CLD_16 CLD_17 CLD_18 CLD_19 CLD_20 CLD_21 LCD I/F CLD_22 CLD_23 CLAC CLCP CLFP CLLP CLLE CLPOWER DDR_ADD_0 DDR_ADD_1 DDR_ADD_2 DDR_ADD_3 DDR_ADD_4 DDR_ADD_5 DDR_ADD_6 DDR I/F DDR_ADD_7 DDR_ADD_8 ...
Page 16
... Y12 AB12 AA12 AB13 Differential lower data strobe AA13 AA11 Output Lower data mask Y13 Lower gate open AB15 AA16 AB16 I/O Data lines Y16 (upper byte) Y15 Y14 AB14 SPEAR-09-H122 Pin type SSTL_2/SSTL_18 Differential SSTL_2/SSTL_18 SSTL_2/SSTL_18 SSTL_2/SSTL_18 Differential SSTL_2/SSTL_18 SSTL_2/SSTL_18 ...
Page 17
... SPEAR-09-H122 Table 2. Pin description by functional group (continued) Group Signal name DDR_DATA_15 DDR_DQS_1 DDR_nDQS_1 DDR_DM_1 DDR_GATE_1 DDR I/F DDR_VREF DDR_COMP_2V5 DDR_COMP_GND DDR_COMP_1V8 DDR2_EN DEV_DP DEV_DM DEV_VBUS HOST1_DP HOST1_DM HOST1_VBUS USB HOST1_OVRC HOST2_DP HOST2_DM HOST2_VBUS HOST2_OVRC USB_RREF MCLK_XI Master Clock MCLK_XO RTC_XI RTC ...
Page 18
... AB18 Input Serial data in Y18 I/O Serial data in/out Y19 I/O Serial clock H19 I/O Data SPEAR-09-H122 Pin type TTL output buffer 3.3 V capable TTL BIDIR buffer 3.3 V capable 3.3 V tolerant, PU TTL output buffer 3.3 V capable TTL input buffer 3.3 V tolerant, PD TTL output buffer 3.3 V capable TTL input buffer 3 ...
Page 19
... SPEAR-09-H122 Table 2. Pin description by functional group (continued) Group Signal name NF_IO_1 NF_IO_2 NF_IO_3 NF_IO_4 NF_IO_5 NF_IO_6 NF_IO_7 NAND FLASH NF_CE I/F NF_RE NF_WE NF_ALE NF_CLE NF_WP NF_RB MRESET PH0 PH0n PH1 PH1n PH2 PH2n PH3 PH3n LVDS PH4 I/F PH4n PH5 PH5n ...
Page 20
... W17 DD DDR_PLL_V T17 DD LVDS_V F11, F12, F14 DD RTC_V B10 DD 20/40 Ball Direction Function General purpose I/O B11 Input with LVDS transceiver E11 Output Configuration Ball SPEAR-09-H122 Pin type LVDS receiver Analog 3.3 V capable Value 3.3 V 1.0 V 2.5 V 1.0 V 3.3 V 2.5 V 1.0 V 3.3 V 2.5 V 1.0 V 3.3 V 1.0 V 2.5 V 1 ...
Page 21
... SPEAR-09-H122 2.2 Special IOs 2.2.1 USB 2.0 transceiver SPEAr Head600 has three USB 2.0 multimode ATX transceivers. One transceiver will be used by the USB device controller, and two will be used by the hosts. These are all integrated into a single USB three-PHY macro. 2.2.2 SSTL_2/SSTL_18 T.B.D. 2.2.3 LVDS T.B.D. Pin description ...
Page 22
... JPEG codec 0xD17F.FFFF IrDA 0xD1FF.FFFF FSMC 0xD27F.FFFF FSMC 0xD7FF.FFFF SRAM SPEAR-09-H122 Notes DDR1 or DDR2 Programmable logic array Low speed connection Application subsystem High speed connection Multi layer CPU subsystem Basic subsystem Notes Reserved NAND Flash controller NAND Flash memory ...
Page 23
... SPEAR-09-H122 3.3 ICM2 - application subsystem Table 6. ICM2 - application subsystem Start address 0xD800.0000 0xD808.0000 0xD810.0000 0xD818.0000 0xD820.0000 0xD828.0000 3.4 ICM4 - high speed connection Table 7. ICM4 - high speed connection Start address 0xE000.0000 0xE080.0000 0xE100.0000 0xE110.0000 0xE120.0000 0xE130.0000 0xE180.0000 0xE190.0000 0xE1A0.0000 0xE200.0000 0xE210.0000 0xE220.0000 0xE280.0000 0xE290 ...
Page 24
... SDRAM controller 0xFC87.FFFF Timer 0xFC8F.FFFF Watch dog timer 0xFC97.FFFF Real time clock 0xFC9F.FFFF General purpose I/O 0xFCA7.FFFF System controller 0xFCAF.FFFF Miscellaneous registers 0xFEFF.FFFF - 0xFFFF.FFFF Internal ROM SPEAR-09-H122 Notes Reserved Reserved Notes Reserved Boot Bus APB APB AHB AHB AHB AHB ...
Page 25
... SPEAR-09-H122 4 Main blocks 4.1 7.1 CPU subsystem 4.1.1 Overview The CPU sub-system includes the following blocks: ● ARM 926EJS ● Two timer channels ● One GPIO block (8 I/O lines) ● Two interrupt controller (32 IRQ lines) 4.1.2 CPU ARM 926EJ-S The processor is the powerful ARM926EJ-S, targeted for multi-tasking applications. ...
Page 26
... The clock system consists of 2 main parts: a multi-clock generator block and an two internal PLL. The multi-clock generator block, starting from a reference signal (which generally is delivered from the PLL), generates all clocks for the IPs of SPEAr Head600 according to dedicated programmable registers. Each PLL, starting from the oscillator input of 30 MHz, generates a clock signal at a frequency corresponding at the highest of the group, which is the reference signal used by the multi-clock generator block to obtain all the other requested clocks for the group ...
Page 27
... SPEAR-09-H122 4.3.2 Crystal equivalent model Figure 4. Crystal equivalent model the parasitic capacitance of the crystal package 2. Cl1 and Cl2 are the capacitance on each resonator PAD Table 10. Main oscillator characteristics Supplier Epson (E31821) Raltron (M3000) KSS (KSS3KF) 4.4 RTC oscillator 4.4.1 RTC crystal connection Figure 5 ...
Page 28
... Main blocks 4.4.2 RTC crystal equivalent model Figure 6. RTC crystal equivalent model the parasitic capacitance of the crystal package 2. Cl1 and Cl2 are the capacitance on each resonator PAD Table 11. RTC oscillator characteristics Supplier Ecliptek 28/ Rm(KOhms) Lm(mH) <65 10 SPEAR-09-H122 Xo 2 GND Cm(fF) Co(pF) 1.9 0.85 ...
Page 29
... AHB master bus width, supporting 32, 64, and 128-bit wide data transactions 4.6 USB2 host controller SPEAr Head600 has two fully independent USB 2.0 hosts and each one is constituted with 5 major blocks: ● EHCI able to manage the high speed transfer (HS - 480 Mbit) ● ...
Page 30
... An AHB master for data transfer to system memory is provided, supporting 8, 16, and 32-bit wide data transactions on the AHB bus ● A USB plug detect (UPD) which detects the connection of a cable 4.8 Low jitter PLL Within the USB hosts and device a local low jitter PLL is provided to meet the USB2.0 specification requirements. 30/40 SPEAR-09-H122 ...
Page 31
... AHB clock (programmable) 4.9.2 Custom project development The flow to develop a custom project to embed in the SPEAr Head600 is similar to the standard ASIC flow. The configurable Logic is an empty module of the whole system-on-chip. Pin out and maximum gates are fixed. The HDL project is synthesized using dedicated library and post synthesis simulation is possible to verify the custom net-list ...
Page 32
... Programmable choice of interface operation SPI, microwire or TI synchronous serial ● Programmable data frame size from 4 to 16-bit ● The SPI controllers can deal with master and slave mode ● A connection with general purpose DMA is provided to reduce the CPU load 32/40 SPEAR-09-H122 ...
Page 33
... SPEAR-09-H122 5 Electrical characteristics 5.1 Absolute maximum ratings This product contains devices to protect the inputs against damage due to high static voltages, however it is advisable to take normal precaution to avoid application of any voltage higher than the specified maximum rated voltages. Table 12. Absolute maximum ratings ...
Page 34
... Supply voltage PLL DD V OSC Supply voltage oscillator DD V DDR1 Supply voltage DRAM I/F (DDR1 DDR2 Supply voltage DRAM I/F (DDR2 RTC Supply voltage RTC DD T Operating temperature OP 34/40 Parameter Min. 0.95 3 2.25 2.25 2.25 1.7 0.95 -40 SPEAR-09-H122 Typ. Max. Unit 1 1.05 V 3.3 3.6 V 2.5 2.75 V 2.5 2.75 V 2.5 2.75 V 1 °C ...
Page 35
... SPEAR-09-H122 5.3 General purpose I/O characteristics The 3.3V I/Os are compliant with JEDEC standard JESD8b Table 14. Low voltage TTL DC input specification (3V<vdde3V3<3.6V) Symbol V Low level input voltage il V High level input voltage ih V Schmitt trigger hysteresis hyst Table 15. Low voltage TTL DC output specification (3V<vdde3V3<3.6V) ...
Page 36
... R Output impedance o 36/40 Voa TX line Z0 Cop Vob TX line Z0 Cop Ω Ω Parameter Parameter Test condition SSTL2 SSTL18 SSTL2 SSTL18 Parameter Test condition SPEAR-09-H122 Rt Test condition Min. Max. 0.4 2.2 -100 +100 idthh idthl 80 120 Min. Max. -0 0.15 ref -0 0.125 ref ...
Page 37
... SPEAR-09-H122 Table 22. On die termination Symbol Termination value of resistance for on (1) RT1 die termination Termination value of resistance for on (1) RT2 die termination 1. For more detail about RT1/RT2 usage refer to chapter 17.4.10 MEM10_CTL Register of the User Manual (register rrt_0). Table 23. Reference voltage ...
Page 38
... MAX. MIN. TYP. MAX. 1.81 0.0713 0.0106 1.305 0.0514 0.52 0.0205 0.785 0.0309 0.50 0.55 0.0177 0.0197 0.0217 23.00 23.20 0.8976 0.9055 0.9134 21.00 0.8268 23.00 23.20 0.8976 0.9055 0.9134 21.00 0.8268 1.00 0.0394 1.00 0.0394 0.20 0.0079 0.25 0.0098 0.10 0.0039 SPEAR-09-H122 OUTLINE AND MECHANICAL DATA PBGA420 (23x23x1.81mm) Ball Grid Array Package 7859856 A ® ...
Page 39
... SPEAR-09-H122 7 Revision history Table 24. Document revision history Date 28-Feb-2007 31-Jul-2008 Revision 1 Initial release. Modified Section 1.1: Modified Table 2: Pin description by functional group Modified Section 4.7: USB2 device 2 Added Section 5.3: General purpose I/O characteristics Added Section 5.4: LVDS electrical characteristics Added Section 5.5: DDR I & DDR II pads electrical characteristics ...
Page 40
... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 40/40 Please Read Carefully: © 2008 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com SPEAR-09-H122 ...