PEX8548-AA25BI PLX [PLX Technology], PEX8548-AA25BI Datasheet
PEX8548-AA25BI
Manufacturer Part Number
PEX8548-AA25BI
Description
High-Performance 48-lane, 9-port PCIe Switch
Manufacturer
PLX [PLX Technology]
Datasheet
1.PEX8548-AA25BI.pdf
(4 pages)
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Features
o 48-lane PCI Express switch
o Up to nine configurable ports
o 37.5mm x 37.5mm,
o Typical Power: 4.9 Watts
o Standard Compliant
o High Performance
o Flexible Configuration
o PCI Express Power Management
o Quality of Service (QoS)
o Reliability, Availability, Serviceability
PEX 8548 General Features
PEX 8548 Key Features
- Integrated SerDes
(x1, x2, x4, x8, x16)
736-ball PBGA package
- PCI Express Base Specification, r1.1
- Non-blocking switch fabric
- Full line rate on all ports
- Packet Cut-Thru with 110ns max
- Nine highly flexible & configurable
- Configurable with strapping pins,
- Lane and polarity reversal
- Link power management states: L0,
- Device states: D0 and D3hot
- One Virtual Channel per port
- Eight Traffic Classes per port
- Weighted Round-Robin Ingress Port
- 3 Standard Hot-Plug Controllers
- Upstream port as hot-plug client
- Transaction Layer end-to-end CRC
- Poison bit
- INTA# interrupt signal
- Fatal Error (FATAL_ERR#) signal
- PCIe baseline error reporting
- Advanced Error Reporting
- Port Status bits and GPO available
- Per port error diagnostics
- JTAG boundary scan
packet latency (x16 to x16)
ports (x1, x2, x4, x8, or x16)
EEPROM, I
L0s, L1, L2/L3 Ready, and L3
Arbitration
(legacy SERR equivalent)
• Bad DLLPs
• Bad TLPs
• CRC errors
Version 1.5 2007
2
C, or Host software
Multi-purpose, High Performance ExpressLane™ Switch
The ExpressLane PEX 8548 device offers PCI Express switching capability
enabling users to add scalable high bandwidth, non-blocking interconnection
to a wide variety of applications including servers, storage systems,
communications platforms, blade servers, and embedded-control
products. The PEX 8548 is well suited for fan-out, aggregation, dual-
graphics, peer-to-peer, and fabric backplane applications.
Highly Flexible Port Configurations
The PEX 8548 offers highly configurable ports. There are a maximum of 9
ports that can be configured to any legal width from x1 to x16, in any
combination to support your specific bandwidth needs. The ports can be
configured for symmetric (each port having the same lane width and traffic
load) or asymmetric (ports having different lane widths) traffic. In the event
of asymmetric traffic, the PEX 8548 features a flexible central packet
memory that allocates a memory buffer for each port as required by the
application or endpoint. This buffer allocation along with the device's
flexible packet flow control minimizes bottlenecks when the upstream and
aggregated downstream bandwidths do not match (are asymmetric). Any of
the ports can be designated as the upstream port, which can be changed
dynamically.
High Performance
The PEX 8548 architecture supports packet cut-thru with a max latency of
110ns (x16 to x16). This, combined with large packet memory (1024 byte
maximum payload size) and non-blocking internal switch architecture,
provide full line rate on all ports for performance-hungry applications such as
storage servers or storage switch fabrics.
End-to-end Packet Integrity
The PEX 8548 provides end-to-end CRC protection (ECRC) and Poison bit
support to enable designs that require end-to-end data integrity. These
features are optional in the PCI Express specification, but PLX provides
them across its entire ExpressLane switch product line.
Configuration Flexibility
The PEX 8548 provides several ways to configure its operations. The device
can be configured through strapping pins, I
cycles, or an optional serial EEPROM. This allows for easy debug during the
development phase, performance monitoring during the operation phase, and
driver or software upgrade.
Interoperability
The PEX 8548 is designed to be fully compliant with the PCI Express Base
Specification r1.1. Additionally, it supports auto-negotiation, lane reversal,
and polarity reversal. The PEX 8548 also undergoes thorough
interoperability testing in PLX’s Interoperability Lab.
High-Performance 48-lane, 9-port PCIe Switch
PEX 8548
2
C interface, CPU configuration
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PEX8548-AA25BI Summary of contents
Page 1
Version 1.5 2007 Features PEX 8548 General Features o 48-lane PCI Express switch - Integrated SerDes nine configurable ports (x1, x2, x4, x8, x16) o 37.5mm x 37.5mm, 736-ball PBGA package o Typical Power: 4.9 Watts PEX ...
Page 2
Low Power with Granular SerDes Control The PEX 8548 provides low power capability that is fully compliant with the PCI Express power management specification. In addition, the SerDes physical links can be turned off when unused for even lower power. ...
Page 3
Figure 2 shows a typical server-based design where the root complex provides a PCI Express link that needs to be expanded to a larger number of smaller ports for a variety of I/O functions. In this example, the PEX 8548 ...
Page 4
... Information supplied by PLX is believed to be accurate and reliable, but PLX Technology, Inc. assumes no responsibility for any errors that may appear in this material. PLX Technology, Inc. reserves the right, without notice, to make changes in product design or specification. PEX8548-SIL-PB-P1-1.5 bus interface (matching bus, device, and function number) ...