PT7C4300 PERICOM [Pericom Semiconductor Corporation], PT7C4300 Datasheet - Page 8

• Manufacturer Part Number: PT7C4300
• Manufacturer: PERICOM [Pericom Semiconductor Corporation]

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Communication
1.
a)
The I
of these two signals is used to transmit and receive communication start/stop signals, data signals, acknowledge signals, and so on.
Both the SCL and SDA signals are held at high level whenever communications are not being performed. The starting and
stopping of communications is controlled at the rising edge or falling edge of SDA while SCL is at high level. During data
transfers, data changes that occur on the SDA line are performed while the SCL line is at low level, and on the receiving side the
data is captured while the SCL line is at high level. In either case, the data is transferred via the SCL line at a rate of one bit per
clock pulse. The I
chip select pin, slave addresses are allocated to each device and the receiving device responds to communications only when its
slave address matches the slave address in the received data.
b)
All ports connected to the I
multiple devices.
SCL and SDA are both connected to the VDD line via a pull-up resistance. Consequently, SCL and SDA are both held at high
level when the bus is released (when communication is not being performed).
PT0222(02/06)
Addr.
(hex)
04
05
06
I
Overview of I
2
System Configuration
C bus supports bi-directional communications via two signal lines: the SDA (data) line and SCL (clock) line. A combination
2
C Bus Interface
SD A
N ote: W hen there is only one m aster, the M CU is ready for driving SCL to "H " and R
SCL
V cc
Months (01-12)
Dates (01-31)
Years (00-99)
Description
(default)
(default)
(default)
R
P
2
C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a
2
C-BUS
R
P
2
C bus must be either open drain or open collector ports in order to enable AND connections to
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Y80
D7
×
×
M aster
M CU
Y40
D6
×
×
Fig.1 System configuration
D20
Y20
D5
×
Slave
R TC
8
M10
D10
Y10
D4
Real-time Clock Module (I
M8
D3
D8
Y8
O ther Peripheral
D evice
P
of SCL m ay not required.
M4
D2
D4
Y4
M2
D1
D2
Y2
Data Sheet
PT7C4300
2
C Bus)
M1
D0
D1
Y1
Ver: 0