RT8206L RICHTEK [Richtek Technology Corporation], RT8206L Datasheet - Page 24

• Manufacturer Part Number: RT8206L
• Description: High Efficiency, Main Power Supply Controller for Notebook Computers
• Manufacturer: RICHTEK [Richtek Technology Corporation]

RT8206L/M
capacitors by a sudden load step. The peak amplitude of
the output transient (V
maximum duty factor, which can be calculated from the
on-time and minimum off-time :
where minimum off-time (t
is from Table 1.
Output Capacitor Selection
The output filter capacitor must have low enough equivalent
series resistance (ESR) to meet output ripple and load-
transient requirements, yet have high enough ESR to
satisfy stability requirements. The output capacitance
must also be high enough to absorb the inductor energy
while transiting from full-load to no-load conditions without
tripping the overvoltage fault latch.
Although Mach Response
provides many advantages such as ease-of-use, minimum
external component configuration, and extremely short
response time, due to not employing an error amplifier in
the loop, a sufficient feedback signal needs to be provided
by an external circuit to reduce the jitter level. The required
signal level is approximately 15mV at the comparing point.
This generates V
node. The output capacitor ESR should meet this
requirement.
Output Capacitor Stability
Stability is determined by the value of the ESR zero relative
to the switching frequency. The point of instability is given
by the following equation :
Do not put high value ceramic capacitors directly across
the outputs without taking precautions to ensure stability.
Large ceramic capacitors can have a high ESR zero
frequency and cause erratic, unstable operation. However,
it is easy to add enough series resistance by placing the
capacitors a couple of inches downstream from the
inductor and connecting VOUTx or the FBx divider close
to the inductor.
Copyright
www.richtek.com
24
V
f
ESR
SAG
=
=
©
2
2012 Richtek Technology Corporation. All rights reserved.
2 C
× ×
×
π
OUT
ESR C
( I
Δ
RIPPLE
1
LOAD
×
×
V
OUTx
)
= (V
OUT
2
SAG
TM
× ×
OFF(MIN)
L
×
DRV
OUT
) is also a function of the
≤
⎡
⎢
⎣
K
⎛
⎜
⎝
f
SW
K
/ 2) x 15mV at the output
⎛
⎜
⎝
TM
4
V
V
) = 300ns (typ.) and K
IN
dual ramp valley mode
OUTx
V
IN
−
V
V
IN
OUTx
+
t
OFF(MIN)
⎞
⎟
⎠
−
t
OFF(MIN)
⎞
⎟
⎠
⎤
⎥
⎦
There are two related but distinct factors, double-pulsing
and feedback loop instability, for unstable operation.
Double-pulsing occurs due to noise on the output or
because the ESR is so low that there is not enough voltage
ramp in the output voltage signal. This “fools” the error
comparator into triggering a new cycle immediately after
the 300ns minimum off-time period has expired. Double-
pulsing is more annoying than harmful, resulting in nothing
worse than increased output ripple. However, it may
indicate the possible presence of loop instability, which
is caused by insufficient ESR.
Loop instability can result in oscillations at the output
after line or load perturbations that can trip the over-voltage
protection latch or cause the output voltage to fall below
the tolerance limit.
The easiest method for checking stability is to apply a
very fast zero-to-max load transient and carefully observe
the output-voltage-ripple envelope for overshoot and ringing.
It helps to simultaneously monitor the inductor current
with an AC current probe. Do not allow more than one
cycle of ringing after the initial step-response under- or
overshoot.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum operation junction temperature. The maximum
power dissipation depends on the thermal resistance of
IC package, PCB layout, the rate of surroundings airflow
and temperature difference between junction to ambient.
The maximum power dissipation can be calculated by
following formula :
P
where T
temperature, T
junction to ambient thermal resistance.
For recommended operating conditions specification, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θ
WQFN-32L 5x5 package, the thermal resistance, θ
36°C/W on a standard JEDEC 51-7 four-layer thermal test
board. The maximum power dissipation at T
be calculated by the following formula :
D(MAX)
is a registered trademark of Richtek Technology Corporation.
= ( T
J(MAX)
J(MAX)
A
is the ambient temperature and θ
is the maximum operation junction
- T
A
) / θ
JA
JA,
DS8206L/M-07 June 2012
is layout dependent. For
A
= 25°C can
JA
is the
JA,
is